RTL validation methodology on high complexity wireless microcontroller using OVM technique for fast time to market

Increased demand in internet of thing (IOT) application based has inadvertently forced the move towards higher complexity of integrated circuit supporting SoC. Such spontaneous increased in complexity poses unequivocal complicated validation strategies. Hence, the complexity allows researchers to co...

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Bibliographic Details
Published in:	EPJ Web of Conferences Vol. 162; p. 1068
Main Authors:	Muhammad, Nurul Zhafirah, Harun, A., Hambali, N.A.M.A., Murad, S. A. Z., Mohyar, S. N., Isa, M.N., Jambek, AB
Format:	Journal Article Conference Proceeding
Language:	English
Published:	Les Ulis EDP Sciences 01-01-2017
Subjects:	Complexity Integrated circuits Internet of Things Markets Methodology Methods Microcontrollers
Online Access:	Get full text
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Summary:	Increased demand in internet of thing (IOT) application based has inadvertently forced the move towards higher complexity of integrated circuit supporting SoC. Such spontaneous increased in complexity poses unequivocal complicated validation strategies. Hence, the complexity allows researchers to come out with various exceptional methodologies in order to overcome this problem. This in essence brings about the discovery of dynamic verification, formal verification and hybrid techniques. In reserve, it is very important to discover bugs at infancy of verification process in (SoC) in order to reduce time consuming and fast time to market for the system. Ergo, in this paper we are focusing on the methodology of verification that can be done at Register Transfer Level of SoC based on the AMBA bus design. On top of that, the discovery of others verification method called Open Verification Methodology (OVM) brings out an easier way in RTL validation methodology neither as the replacement for the traditional method yet as an effort for fast time to market for the system. Thus, the method called OVM is proposed in this paper as the verification method for larger design to avert the disclosure of the bottleneck in validation platform.
ISSN:	2100-014X 2101-6275 2100-014X
DOI:	10.1051/epjconf/201716201068