Search Results - "Mouis, M"

Revisited parameter extraction methodology for electrical characterization of junctionless transistors by Jeon, D.-Y., Park, S.J., Mouis, M., Berthomé, M., Barraud, S., Kim, G.-T., Ghibaudo, G.

“…► Conventional parameter extraction methodologies were revisited for the electrical characterization of JLT devices. ► Interestingly, two slopes in the…”
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Carrier transport in HfO2/metal gate MOSFETs : Physical insight into critical parameters by CASSE, Mikaël, THEVENOD, Laurent, BILLON, Thierry, MOUIS, Mireille, BOULANGER, Fabien, GUILLAUMOT, Bernard, TOSTI, Lucie, MARTIN, Francois, MITARD, Jérome, WEBER, Olivier, ANDRIEU, Francois, ERNST, Thomas, REIMBOLD, Gilles

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Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs by Buran, C., Pala, M.G., Bescond, M., Dubois, M., Mouis, M.

“…We address the transport properties of narrow gate-all-around silicon nanowires in the presence of surface-roughness (SR) scattering at the Si/SiO 2 interface,…”
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Calculations of hole mass in [1 1 0]-uniaxially strained silicon for the stress-engineering of p-MOS transistors by Guillaume, T., Mouis, M.

“…The influence of stress on transport properties in p-MOSFETs is rather well known for the case of biaxially strained channels obtained using hetero-epitaxy…”
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DC and low frequency noise characterization of FinFET devices by Bennamane, K., Boutchacha, T., Ghibaudo, G., Mouis, M., Collaert, N.

“…A detailed DC and LF noise characterization of FinFETs is carried out. Parameter extraction conducted at room and low temperature clearly indicates that the…”
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An accelerated algorithm for 2D simulations of the quantum ballistic transport in nanoscale MOSFETs by Ben Abdallah, N., Mouis, M., Negulescu, C.

“…An accelerated algorithm for the resolution of the coupled Schrödinger/Poisson system, with open boundary conditions, is presented. This method improves the…”
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Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance by Widiez, J., Lolivier, J., Vinet, M., Poiroux, T., Previtali, B., Dauge, F., Mouis, M., Deleonibus, S.

“…Using a novel process flow, we managed to cointegrate several devices on the same wafer; single gate (SG), ground plane (GP), perfectly aligned double gate…”
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A new method for the extraction of flat-band voltage and doping concentration in Tri-gate Junctionless Transistors by Jeon, D.-Y., Park, S.J., Mouis, M., Barraud, S., Kim, G.-T., Ghibaudo, G.

“…► We report a new parameter extraction method for Junctionless Transistors (JLTs). ► Flat-band voltage (Vfb) of Tri-gate JLT devices was extracted by the new…”
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Piezoresistance effect of strained and unstrained fully-depleted silicon-on-insulator MOSFETs integrating a HfO2/TiN gate stack by ROCHETTE, F, CASSE, M, MOUIS, M, HAZIOT, A, PIOGER, T, GHIBAUDO, G, BOULANGER, F

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Experimental characterization of the subthreshold leakage current in triple-gate FinFETs by Tsormpatzoglou, A., Dimitriadis, C.A., Mouis, M., Ghibaudo, G., Collaert, N.

“…The gate and subthreshold drain leakage currents are investigated experimentally in triple-gate FinFETs for power supply voltage V dd = 1 V. The gate and drain…”
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Study of annealing temperature influence on the performance of top gated graphene/SiC transistors by Clavel, M., Poiroux, T., Mouis, M., Becerra, L., Thomassin, J.L., Zenasni, A., Lapertot, G., Rouchon, D., Lafond, D., Faynot, O.

“…► We used a 20nm ALD alumina layer as high-k gate dielectric on graphene. ► Annealed alumina dielectric prevents graphene from adsorbing impurities. ► This…”
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Modeling of remote Coulomb scattering limited mobility in MOSFET with HfO2/SiO2 gate stacks by BARRAUD, S, THEVENOD, L, CASSE, M, BONNO, O, MOUIS, M

“…The reduction of electron mobility in MOSFET with HfO2/SiO2 gate stack is analyzed using a model for remote Coulomb scattering (RCS) due to charges fixed at…”
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Differential magnetoresistance technique for mobility extraction in ultra-short channel FDSOI transistors by Chaisantikulwat, W., Mouis, M., Ghibaudo, G., Gallon, C., Fenouillet-Beranger, C., Maude, D.K., Skotnicki, T., Cristoloveanu, S.

“…Ultra-thin Silicon-on-Insulator (SOI) transistor has proved to offer advantages over bulk MOSFETs for high-speed, low power applications. However, there is…”
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Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique by Chaisantikulwat, W., Mouis, M., Ghibaudo, G., Cristoloveanu, S., Widiez, J., Vinet, M., Deleonibus, S.

“…Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a…”
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Experimental evidence and extraction of the electron mass variation in [1 1 0] uniaxially strained MOSFETs by Rochette, F., Cassé, M., Mouis, M., Reimbold, G., Blachier, D., Leroux, C., Guillaumot, B., Boulanger, F.

“…In this paper, we investigate electron mobility enhancement in [1 1 0] uniaxially strained nMOSFETs with three different channel orientations on a [0 0 1] Si…”
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Strain sensitivity of gate leakage in strained-SOI nMOSFETs: A benefit for the performance trade-off and a novel way to extract the strain-induced band offset by Rochette, F., Garros, X., Reimbold, G., Andrieu, F., Cassé, M., Mouis, M., Ghibaudo, G., Boulanger, F.

“…The impact of biaxial stress on gate leakage is investigated on fully-depleted silicon-on-insulator (FD-SOI) nMOS transistors, integrating either a standard…”
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Mechanical simulation of stress engineering solutions in highly strained p-type FDSOI MOSFETs for 14-nm node and beyond by Oudrhiri, A. Idrissi-El, Martinie, S., Barbe, J.-C, Rozeau, O., Le Royer, C., Jaud, M.-A, Lacord, J., Bernier, N., Grenouillet, L., Rivallin, P., Pelloux-Prayer, J., Casse, M., Mouis, M.

“…Stress engineering is a powerful tool to enhance nanoscale device performances. In this study we developed a methodology of 14nm strained pMOS FDSOI device…”
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Full-three dimensional quantum approach to evaluate the surface-roughness-limited magnetoresistance mobility in SNWT by Buran, C., Pala, M. G., Bescond, M., Mouis, M.

“…We present a theoretical method to simulate magnetotransport in silicon nanowire (Si-NW) MOSFET including the effect of Surface Roughness (SR). We use a full…”
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Influence of TiN metal gate on Si/SiO2 surface roughness in N and PMOSFETs by Thevenod, L., Cassé, M., Mouis, M., Reimbold, G., Fillot, F., Guillaumot, B., Boulanger, F.

“…In this article, we report the influence of TiN gate on electron and hole channel mobility at low temperatures down to 13K. TiN gate is found to modify the…”
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Ultrathin Nanogenerators as Self-Powered/Active Skin Sensors for Tracking Eye Ball Motion by Lee, Sangmin, Hinchet, Ronan, Lee, Yean, Yang, Ya, Lin, Zong-Hong, Ardila, Gustavo, Montès, Laurent, Mouis, Mireille, Wang, Zhong Lin

“…Ultrathin piezoelectric nanogenerator (NG) with a total thickness of ≈16 μm is fabricated as an active or self‐powered sensor for monitoring local deformation…”
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