Search Results - "Mosalikanti, Praveen"

Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking by Kurd, N., Mosalikanti, P., Neidengard, M., Douglas, J., Kumar, R.

“…This paper describes the core and I/O clocking architecture of the next generation Intel reg Coretrade micro-architecture processor (Nehalem), designed on a 45…”
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Haswell: A Family of IA 22 nm Processors by Kurd, Nasser, Chowdhury, Muntaquim, Burton, Edward, Thomas, Thomas P., Mozak, Christopher, Boswell, Brent, Mosalikanti, Praveen, Neidengard, Mark, Deval, Anant, Khanna, Ashish, Chowdhury, Nasirul, Rajwar, Ravi, Wilson, Timothy M., Kumar, Rajesh

“…We describe the 4th Generation Intel® Core™ processor family (codenamed "Haswell") implemented on Intel® 22 nm technology and intended to support form factors…”
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29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation by Mosalikanti, Praveen, Wang, Qi, Shen, Kuan-Yueh James, Neidengard, Mark, Farooq, Syed Feruz Syed, Grossnickle, Vaughn, Kurd, Nasser

“…We present a 0.4-to-6.5GHz Frequency Locked Loop (FLL) implemented in 10nm CMOS, targeting high performance SoCs that require uninterrupted, overshoot-free…”
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A Family of 32 nm IA Processors by Kurd, Nasser A, Bhamidipati, Subramani, Mozak, Chris, Miller, Jeffrey L, Mosalikanti, Praveen, Wilson, Timothy M, El-Husseini, Ali M, Neidengard, Mark, Aly, Ramy E, Nemani, Mahadev, Chowdhury, Muntaquim, Kumar, Rajesh

“…Westmere is the latest IA processor family for mobile, desktop and server market segments, implemented on Intel's second-generation high-k metal gate 32 nm…”
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A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology by Lotfy, Amr, Farooq, Syed Feruz Syed, Wang, Qi S., Yaldiz, Soner, Mosalikanti, Praveen, Kurd, Nasser

“…This paper presents a System-Verilog behavioral model for charge-pump PLLs based on piece-wise constant (PWC) real number modeling and table lookup. The…”
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Next Generation Intel® CoreTM Micro-Architecture (Nehalem) Clocking by KURD, Nasser, MOSALIKANTI, Praveen, NEIDENGARD, Mark, DOUGLAS, Jonathan, KUMAR, Rajesh

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Low power analog circuit techniques in the 5th generation intel coreTM microprocessor (broadwell) by Mosalikanti, Praveen, Kurd, Nasser, Mozak, Chris, Oshita, Takao

“…Fabricated on a 14nm process technology node, the Intel Core TM M and the 5 th generation Core TM processors (code named Broadwell) improve energy efficiency…”
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Next generation Intel® micro-architecture (Nehalem) clocking architecture by Kurd, N., Douglas, J., Mosalikanti, P., Kumar, R.

“…This paper describes the next generation Intel reg micro-architecture (Nehalem) 45 nm IA processorpsilas core and I/O clocking architecture. Among the…”
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High performance DDR architecture in Intel® Core™ processors using 32nm CMOS high-K metal-gate process by Mosalikanti, P, Mozak, C, Kurd, N

“…This paper describes the DDR architecture in Intel® Core™ processors operating up to 1333MT/s and designed in 32nm process technology. The architecture uses…”
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