Search Results - "Morifuji, E."

Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs by Morifuji, E., Yoshida, T., Kanda, M., Matsuda, S., Yamada, S., Matsuoka, F.

“…The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low…”
Get full text

Power Optimization for SRAM and Its Scaling by Morifuji, E., Patil, D., Horowitz, M., Nishi, Y.

“…With technology scaling, there is a strong demand for smaller cell size, higher speed, and lower power in SRAMs. In addition, there are severe constraints for…”
Get full text

Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique by Morifuji, E., Aikawa, H., Yoshimura, H., Sakata, A., Ohta, M., Iwai, M., Matsuoka, F.

“…Layout dependences for stress-enhanced MOSFETs including contact positioning, the second neighboring poly effect, and bent diffusion are modeled in 45-nm CMOS…”
Get full text

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs by Jung-Suk Goo, Chang-Hoon Choi, Danneville, F., Morifuji, E., Momose, H.S., Zhiping Yu, Iwai, H., Lee, T.H., Dutton, R.W.

“…Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for…”
Get full text

Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide by Momose, H.S., Nakamura, S.-I., Ohguro, T., Yoshitomi, T., Morifuji, E., Morimoto, T., Katsumata, Y., Iwai, H.

“…Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there…”
Get full text

Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS by Momose, H.S., Morifuji, E., Yoshitomi, T., Ohguro, T., Saito, M., Iwai, H.

“…The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO/sub 2/ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were…”
Get full text

New guideline of Vdd and Vth scaling for 65nm technology and beyond by Morifuji, E., Yoshida, T., Tsuno, H., Kikuchi, Y., Matsuda, S., Yamada, S., Noguchi, T., Kakumu, M.

“…We show new guideline of Vdd and Vth scaling for logic blocks and high density SRAM cell from low power dissipation viewpoint. New degradation mode for…”
Get full text

Ultrathin gate oxide CMOS with nondoped selective epitaxial Si channel layer by Momose, H.S., Ohguro, T., Morifuji, E., Sugaya, H., Nakamura, S., Iwai, H.

“…The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and…”
Get full text

Thermal stability of CoSi/sub 2/ film for CMOS salicide by Ohguro, T., Saito, M., Morifuji, E., Yoshitomi, T., Morimoto, T., Momose, H.S., Katsumata, Y., Iwai, H.

“…We describe the relationship between the sheet resistance of Co-silicided poly-Si and various doping elements. The surface condition of the poly-Si before Co…”
Get full text

Power Si-MOSFET operating with high efficiency under low supply voltage by Ohguro, T., Saito, M., Morifuji, E., Murakami, K., Matsuzaki, K., Yoshitomi, T., Morimoto, T., Momose, H.S., Katsumata, Y., Iwai, H.

“…A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages…”
Get full text

Technology independent degradation of minimum noise figure due to pad parasitics by Biber, C.E., Schmatz, M.L., Morf, T., Lott, U., Morifuji, E., Bachtold, W.

“…In order to investigate the influence of pad parasitics on device noise performance, noise parameters on Si CMOS, GaAs MESFET and GaAs p-HEMT transistors were…”
Get full text

Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique by Aikawa, H., Morifuji, E., Sanuki, T., Sawada, T., Kyoh, S., Sakata, A., Ohta, M., Yoshimura, H., Nakayama, T., Iwai, M., Matsuoka, F.

“…Gate density is ultimately increased to 2100 kGates/mm 2 by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout…”
Get full text

High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs by Momose, H.S., Morifuji, E., Yoshitomi, T., Ohguro, T., Saito, I., Morimoto, T., Katsumata, Y., Iwai, H.

“…Results of the high-frequency AC characteristics of 1.5 nm direct-tunneling gate oxide MOSFET's were shown for the first time. Very high cutoff frequencies of…”
Get full text

Electro-Thermally Coupled Power Optimization for Future Transistors and Its Applications by Kuo-An Chao, Andy, Kapur, Pawan, Morifuji, Eiji, Saraswat, Krishna, Nishi, Yoshio

“…We report a novel electro-thermally coupled power-optimization methodology for future transistors. The methodology self-consistently yields the globally…”
Get full text

New guideline for hydrogen treatment in advanced system LSI by Morifuji, E., Kumamori, T., Muta, M., Suzuki, K., Krishnan, M.S., Brozek, T., Li, X., Asano, W., Nishigori, M., Yanagiya, N., Yamada, S., Miyamoto, K., Noguchi, T., Kakumu, M.

“…In this paper, we focus on hydrogen related processes and its impact on system LSI. Hydrogen affects not only DRAM performance but also reliability…”
Get full text

Nitrogen-doped nickel monosilicide technique for deep submicron CMOS salicide by Ohguro, T., Nakamura, S., Morifuji, E., Ono, M., Yoshitomi, T., Saito, M., Momose, H.S., Iwai, H.

“…A nitrogen-doped NiSi technique has been developed for deep submicron CMOS. It was found that the nitrogen suppresses oxidation of the silicide film, resulting…”
Get full text

New considerations for highly reliable PMOSFETs in 100 nm generation and beyond by Morifuji, E., Kumamori, T., Muta, M., Suzuki, K., De, I., Shibkov, A., Saxena, S., Enda, T., Aoki, N., Asano, W., Otani, H., Nishigori, M., Miyamoto, K., Matsuoka, F., Noguchi, T., Kakumu, M.

“…The hot-carrier (HC) instability for surface channel PMOSFETs is investigated intensively. We found from experimental data that hot-carrier injection occurs at…”
Get full text

A study of hot-carrier degradation in n- and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime by Momose, H.S., Nakamura, S.-I., Ohguro, T., Yoshitomi, T., Morifuji, E., Morimoto, T., Katsumata, Y., Iwai, H.

“…Hot-carrier degradation in the direct-tunneling regime of the gate oxide was investigated under a wide range of conditions such as stress bias, oxide…”
Get full text

Thermal stability of CoSi2 film for CMOS salicide by Ohguro, T, Saito, M, Morifuji, E, Yoshitomi, T, Morimoto, T, Momose, H.S, Katsumata, Y, Iwai, H

“…The surface condition of the poly-Si before Co sputtering plays an important role in suppressing the "narrow line effect," in which the silicide sheet…”
Get full text

A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime by Momose, H.S., Kimijima, H., Ishizuka, S., Miyahara, Y., Ohguro, T., Yoshitomi, T., Morifuji, E., Nakamura, S., Morimoto, T., Katsumata, Y., Iwai, H.

“…Flicker noise characteristics of 1.5 nn direct-tunneling gate oxide n- and pMOSFETs have been investigated It was confirmed that in the shorter gate length…”
Get full text