Search Results - "Moreno, R.L."

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  1. 1

    An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing by Ferreira, L.H.C., Pimenta, T.C., Moreno, R.L.

    “…An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented. The topology…”
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    Journal Article
  2. 2

    Embolización de arterias uterinas como tratamiento de la hemorragia obstétrica by Nogueira García, J, Moreno Selva, R.L, Ruiz Sánchez, E, Peinado Rodenas, J, Pedrosa Jiménez, M.J, Gómez García, T, González de Merlo, G

    “…Resumen Objetivo Describir los casos de hemorragia obstétrica que han precisado embolización de arterias uterinas (EAU), evaluando la eficacia de dicha técnica…”
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    Journal Article
  3. 3

    A murine model for the study of immune memory in response to pneumococcal conjugate vaccination by Moreno, R.L, Sampson, J.S, Romero-Steiner, S, Wong, B, Johnson, S.E, Ades, E, Carlone, G.M

    Published in Vaccine (13-08-2004)
    “…We developed a murine model for assessment of immunological memory and antibody-induced protection to nasopharyngeal (NP) challenges. BALB/c female mice ( n=10…”
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    Journal Article
  4. 4

    An auto-zero sample-and-hold circuit in 0.8 μm CMOS by Ferreira, L.H.C., Pimenta, T.C., Moreno, R.L.

    “…This work describes the silicon implementation of a new sample-and-hold circuit topology. The main feature of the circuit is its auto-zero capability. The…”
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    Conference Proceeding
  5. 5

    Design of a measurement and interface integrated circuit for characterization of switched current memory cells by Pereira, A.M., Pimenta, T.C., Moreno, R.L., Charry R, E., Jorge, A.M.

    “…Dynamic current mirrors, or SI current cells, are widely used in analog signal processing circuits. They could be implemented using a standard cell methodology…”
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    Conference Proceeding
  6. 6

    Design Considerations of Class D Amplifier Suitable Hearing Aid Devices by Ruiz, D.N., Moreno, R.L., Pimenta, T.C.

    “…This paper describes the design of a class D amplifier for hearing aid devices using PWM modulation technique. The new topology used to overcome offset…”
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    Conference Proceeding
  7. 7

    A 1.6GHz Downconverter Mixer in 0.25μm CMOS by Antunes, F.J., Pimenta, T.C., Moreno, R.L.

    “…This work shows the implementation of a CMOS double balanced mixer based in the Gilbert cell capable of providing high conversion gain and high linearity. The…”
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    Conference Proceeding
  8. 8

    A 0.25μm CMOS Downconverter Mixer for 1.6GHz by Antunes, F.J., Pimenta, T.C., Moreno, R.L.

    “…This work shows the implementation of a CMOS double balanced mixer based in the Gilbert cell capable of providing high conversion gain and high linearity. The…”
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    Conference Proceeding
  9. 9

    The design of a digital IC for thyristor triggering by Pimenta, T.C., Vermaas, L.L.G., Crepaldi, P.C., Moreno, R.L.

    “…This paper presents the functional description and the design of a fully digital integrated circuit for thyristor firing control in a 1 /spl mu/m CMOS…”
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    Conference Proceeding
  10. 10

    A CMOS low noise amplifier for biomedical telemetry applications by Moreno, R.L., Rodrigues, E.C.

    “…This paper describes a 200 MHz inductorless low-noise amplifier (LNA) fabricated in a standard digital 0.35-/spl mu/m AMS CMOS process. The LNA has been…”
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    Conference Proceeding
  11. 11

    A bandgap voltage reference using digital CMOS process by Vermaas, L.L.G., De Mori, C.R.T., Moreno, R.L., Pereira, A.M., Charry R., E.

    “…This work describes some issues and criteria for the design of a bandgap voltage reference. It examines a particular voltage reference architecture,…”
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    Conference Proceeding
  12. 12

    A precise sample-and-hold circuit topology in CMOS for low voltage applications with offset voltage self correction by Ferreira, L.H.C., Moreno, R.L., Pimenta, T.C., Filho, C.A.R.

    “…This work describes a new topology for CMOS sample-and-hold circuits in low voltage with self-correction of the offset voltage caused by mismatches in the…”
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    Conference Proceeding
  13. 13

    An offset self-correction sample and hold circuit for precise applications in low voltage CMOS by Ferreira, L.H.C., Moreno, R.L., Pimenta, T.C., Filho, C.A.R.

    “…This work describes a new topology for CMOS sample-and-hold circuits, in low voltage, with self-correction of the offset voltage caused by mismatches in the…”
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    Conference Proceeding
  14. 14

    An offset self-correction sample and hold circuit for precise applications in low voltage CMOS by Ferreira, L.H.C., Moreno, R.L., Pimenta, T.C., Filho, C.A.R.

    “…This work describes a new topology for CMOS sample-and-hold circuits, in low voltage, with self-correction of the offset voltage caused by mismatches in the…”
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    Conference Proceeding
  15. 15

    A precise sample-and-hold circuit topology in CMOS for low voltage applications with offset voltage self correction by Henrique, L., Ferreira, C., Moreno, R.L., Pimenta, T.C., Filho, C.A.R.

    “…This work describes a new topology for CMOS sample-and-hold circuits in low voltage with self-correction of the offset voltage caused by mismatches in the…”
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    Conference Proceeding