Search Results - "Mooney, V. J."

Automated bus generation for multiprocessor SoC design by Kyeong Keol Ryu, Mooney, V.J.

“…The performance of a multiprocessor system heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom…”
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Sleepy Stack Leakage Reduction by Jun Cheol Park, Mooney, V.J.

“…Leakage power consumption of current CMOS technology is already a great challenge. International Technology Roadmap for Semiconductors projects that leakage…”
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A hardware-software real-time operating system framework for SoCs by Mooney, V.J., Blough, D.M.

“…The /spl delta/ framework for RTOS-SoC codesign helps designers simultaneously build a SoC or platform-ASIC architecture and a customized hardware-software…”
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An approach to energy-error tradeoffs in approximate ripple carry adders by Kedem, Z. M., Mooney, V. J., Muntimadugu, K. K., Palem, K. V.

“…Given a 16-bit or 32-bit overclocked ripple-carry adder, we minimize error by allocating multiple supply voltages to the gates. We solve the error minimization…”
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A comparison of five different multiprocessor SoC bus architectures by Kyeong Keol Ryu, Eung Shin, Mooney, V.J.

“…The performance of a system, especially multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus…”
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A Novel Parallel Banker's Algorithm for System-on-a-Chip by Lee, J.J., Mooney, V.J.

“…This article proposes a novel O(n) Parallel Banker's Algorithm (PBA), which is a parallelized version of the Banker's Algorithm (BA), a well-known O(m\times n)…”
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A comparison of the RTU hardware RTOS with a hardware/software RTOS by Jaehwan Lee, Mooney, V.J., Daleby, A., Ingstrom, K., Klevin, T., Lindh, L.

“…In this paper, we show the performance comparison and analysis result among three RTOSs: the real-time unit (RTU) hardware RTOS (real-time operating system),…”
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Adaptability, extensibility and flexibility in real-time operating systems by Kuacharoen, P., Akgul, T., Mooney, V.J., Madisetti, V.K.

“…In this paper, we present a mechanism for runtime updating of all kernel modules of a highly modular dynamic real-time operating system. Our approach can help…”
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Low Power Probabilistic Floating Point Multiplier Design by Gupta, A., Mandavalli, S., Mooney, V. J., Keck-Voon Ling, Basu, A., Johan, H., Tandianus, B.

“…We present a low power probabilistic floating point multiplier. Probabilistic computation has been shown to be a technique for achieving energy efficient…”
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Modeling multi-output filtering effects in PCMOS by Singh, A, Basu, A, Ling, K, Mooney, V J

“…A methodology has been proposed recently to predict error rates of cascade structures of blocks in Probabilistic CMOS (PCMOS). It requires characterization of…”
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A novel and fast method for characterizing noise based PCMOS circuits by Singh, A., Mandavalli, S., Mooney, V. J., Ling, K-V

“…Quick and accurate error-rate prediction of Probabilistic CMOS (PCMOS) circuits is crucial for their systematic design and performance evaluation. While still…”
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Low Power Motion Estimation with Probabilistic Computing by Dhoot, C., Mooney, V. J., Lap Pui Chau, Chowdhury, S. R.

“…As Moore's law approaches the low nanometer range, predictions have been made that computing via future technology nodes may no longer be correct due to, for…”
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The system-on-a-chip lock cache by Akgul, B E S, Mooney III, V J

“…Lock synchronization overheads may be significant in a shared-memory multiprocessor system-on-a-chip (SoC) implementation. These overheads are observed in…”
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Timing analysis for preemptive multi-tasking real-time systems with caches by Yudong Tan, Mooney, V.J.

“…In this paper, we propose an approach to estimate the worst case response time (WCRT) of tasks in a preemptive multi-tasking single-processor real-time system…”
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A fast assembly level reverse execution method via dynamic slicing by Akgul, T., Mooney, V.J., Pande, S.

“…One of the most time consuming parts of debugging is trying to locate a bug. In this context, there are two powerful debugging aids which shorten debug time…”
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Automated Bus Generation for Multiprocessor SoC Design by Ryu, Kyeong Keol, Mooney III, Vincent J.

“…The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology…”
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Hardware/software co-design of run-time schedulers for real-time systems by Mooney, Vincent John I I I, De Micheli, Giovanni

“…We present the SERRA Run-Time Scheduler Synthesis and Analysis Tool which automatically generates a run-time scheduler from a heterogeneous system-level…”
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Hardware/Software Partitioning of Operating Systems by Mooney III, Vincent J.

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System-on-a-chip processor synchronization support in hardware by Saglam, B.E., Mooney, V.J.

“…For scalable-shared memory multiprocessor System-on-a-Chip implementations, synchronization overhead may cause catastrophic stalls in the system. Efficient…”
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PARLAK: Parametrized Lock Cache Generator by Akgul, Bilge E. S., Mooney, Vincent J.

“…A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor…”
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