Search Results - "Moo-Kyoung Chung"
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Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-11-2013)“…There has been extensive research on mapping and scheduling tasks on a many-core SoC. However, none considers the optimization of communication types, which…”
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Journal Article -
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Enhancing performance of HW/SW cosimulation and coemulation by reducing communication overhead
Published in IEEE transactions on computers (01-02-2006)“…For system-level simulation of a complex system-on-chip design, multiple hardware simulators and emulators can be combined to work together. The simulation…”
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Journal Article -
3
Lossless frame memory recompression for video codec preserving random accessibility of coding unit
Published in IEEE transactions on consumer electronics (01-11-2009)“…In recent video applications such as MPEG or H.264/AVC, the bandwidth requirement for frame memory has become one of the most critical problems. Compressing…”
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Journal Article -
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Efficient code compression for coarse grained reconfigurable architectures
Published in 2012 IEEE 30th International Conference on Computer Design (ICCD) (01-09-2012)“…Though Coarse Grained Reconfigurable Architecture (CGRA) is a flexible alternative for high performance computing, it has a crucial problem on instruction code…”
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Conference Proceeding
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Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors
Published in 2012 IEEE 30th International Conference on Computer Design (ICCD) (01-09-2012)“…This paper explores high-bandwidth data cache designs for a coarse-grained reconfigurable architecture processor family capable of achieving a high degree of…”
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Conference Proceeding -
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SimParallel: A high performance parallel SystemC simulator using hierarchical multi-threading
Published in 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (01-06-2014)“…As the system complexity increases, the simulation performance becomes one of the most important issues in virtual prototyping. Parallel simulation is a…”
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Conference Proceeding -
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Implementation of a volume rendering on coarse-grained reconfigurable multiprocessor
Published in 2012 International Conference on Field-Programmable Technology (01-12-2012)“…In this paper, we present reconfigurable multiprocessor architecture for volume rendering. The multiprocessor consists of sixteen reconfigurable processors to…”
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Conference Proceeding -
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A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation
Published in Design, Automation and Test in Europe (07-03-2005)“…This paper presents a scheme for efficient channel usage between simulator and accelerator where the accelerator models some RTL sub-blocks in the…”
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Conference Proceeding -
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Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures
Published in 2013 International Conference on Field-Programmable Technology (FPT) (01-12-2013)“…Coarse Grained Reconfigurable Architecture (CGRA) achieves high performance by exploiting instruction-level parallelism with software pipeline. Large…”
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Conference Proceeding -
10
Low latency variable length coding scheme for frame memory recompression
Published in 2010 IEEE International Conference on Multimedia and Expo (01-07-2010)“…In frame memory recompression, decompression latency consists of two components, i.e., memory access cycles for compressed data fetch, and decompression time…”
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Conference Proceeding -
11
Pipeline power reduction through single comparator-based clock gating
Published in 2009 International SoC Design Conference (ISOCC) (01-11-2009)“…Enable-based Clock Gating (ECG) during synthesis to reduce the pipeline power consumption is widely used in scaled technologies. However, the ECG does not…”
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Conference Proceeding -
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Novel RT level methodology for low power by using wasting toggle rate based clock gating
Published in 2009 International SoC Design Conference (ISOCC) (01-01-2009)“…In this paper, we propose a RT level power reduction scheme which can be used for the applications that require ultra-low power consumption. A novel…”
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Conference Proceeding -
13
Improving Lookahead in Parallel Multiprocessor Simulation Using Dynamic Execution Path Prediction
Published in 20th Workshop on Principles of Advanced and Distributed Simulation (PADS'06) (24-05-2006)“…Simulation performance is dominated by lookahead in null message-based conservative time management of parallel discrete event simulation (PDES). This paper…”
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Conference Proceeding -
14
Cache Miss-Aware Dynamic Stack Allocation
Published in 2007 IEEE International Symposium on Circuits and Systems (ISCAS) (01-05-2007)“…Reducing cache misses without increasing cache associativity is critical for reducing the power consumption and cache access time. This paper has focused on…”
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Conference Proceeding -
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SeSCG: Selective sequential clock gating for ultra-low-power multimedia mobile processor design
Published in 2010 IEEE International Conference on Electro/Information Technology (01-05-2010)“…For ultra-low-power multimedia mobile processor (MMP) design, clock-power reduction is critical because the largest portion of the total power (more than 60%…”
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Conference Proceeding -
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Improvement of compiled instruction set simulator by increasing flexibility and reducing compile time
Published in Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004 (2004)“…Although static compiled instruction set simulators (ISSs) are much faster than the interpretive ISSs, they are barely used owing to the restrictions on…”
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Conference Proceeding -
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Performance improvement of multiprocessor simulation by optimizing synchronization and communication
Published in 16th IEEE International Workshop on Rapid System Prototyping (RSP'05) (2005)“…This paper presents fast co-simulation techniques aimed at multiprocessor-based system-on-chip (SoC) design. Unlike existing co-simulation tools that use a…”
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Conference Proceeding -
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Reducing Transaction-Level Modeling Effort while Retaining Low Communication Overhead for HW/SW Co-Emulation System
Published in 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (01-04-2007)“…This paper presents a new scheme that reduces the modeling efforts of a transactor while retaining the performance of transaction-based verification for…”
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Conference Proceeding -
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Cycle-accurate Verification of AHB-based RTL IP with Transaction-level System Environment
Published in 2006 International Symposium on VLSI Design, Automation and Test (01-04-2006)“…This paper presents cycle-accurate mixed-level simulation and acceleration method. This enables us to utilize transaction-level test vectors which are usually…”
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Conference Proceeding -
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System-level performance analysis of embedded system using behavioral C/C++ model
Published in 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT) (2005)“…Design iteration time in SoC design flow is reduced through performance exploration at a higher level of abstraction. This paper proposes an accurate and fast…”
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Conference Proceeding