Search Results - "Montoye, R."

Second-generation RISC floating point with multiply-add fused by Hokenek, E., Montoye, R.K., Cook, P.W.

“…A 440000-transistor second-generation RISC (reduced instruction set computer) floating-point chip is described. The pipeline latency is only two cycles, and a…”
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An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches by Chang, L., Montoye, R.K., Nakamura, Y., Batson, K.A., Eickemeyer, R.J., Dennard, R.H., Haensch, W., Jamsek, D.

“…An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be…”
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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons by Seo, J., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., Rajendran, B., Tierno, J. A., Chang, L., Modha, D. S., Friedman, D. J.

“…Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the…”
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A double precision floating point multiply by Montoye, R., Belluomini, W., Ngo, H., McDowell, C., Sawada, J., Nguyen, T., Veraa, B., Wagoner, J., Lee, M.

“…A 2.2GHz 53/spl times/54 bit pipelined multiplier is fabricated in 130nm CMOS technology with an area of 0.15mm/sup 2/. The circuit implementation results in a…”
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Design-performance trade-offs in CMOS-domino logic by Oklobdzija, V.G., Montoye, R.K.

“…The authors present a study of the charge-sharing problem and its effect on the performance of CMOS-domino logic. Several solutions to the charge-sharing…”
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Matrix-matrix multiplication on a large register file architecture with indirection by Sreedhar, Dheeraj, Derby, J. H., Montoye, R. K., Johnson, C. L.

“…Dense matrix-matrix multiply is an important kernel in many high performance computing applications including the emerging deep neural network based cognitive…”
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Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure by Sreedhar, D., Derby, J. H., Vega, A. J., Rogers, B., Johnson, C. L., Montoye, R. K.

“…The high speed uplink packet access (HSUPA) wireless standard requires extremely high-performance signal processing in the baseband receiver, the most…”
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A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI by Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Montoye, R., Chang, L., Tierno, J., Friedman, D.

“…Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and…”
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A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation by Ditlow, G S, Montoye, R K, Storino, S N, Dance, S M, Ehrenreich, S, Fleischer, B M, Fox, T W, Holmes, K M, Mihara, J, Nakamura, Y, Onishi, S, Shearer, R, Wendel, D, Leland Chang

“…In multi-ported register files, memory cell size grows quadratically with the total number of ports due to wordline and bitline wiring. Reducing the number of…”
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A 64b 4-issue out-of-order execution RISC processor by Shen, G., Patkar, N., Ando, H., Chang, D., Chen, C., Chien Chen, Chen, F., Forssell, P., Gmuender, J., Kitahara, T., Hungwen Li, Lyon, D., Montoye, R., Peng, L., Savkar, S., Sherred, J., Simone, M., Swami, R., Tovey, D., Williams, T.

“…This processor is the first implementation of the SPARC V9 64b instruction set architecture and has an estimated performance exceeding 256 SPECint92 and 330…”
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Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor by Vega, A., Bose, P., Buyuktosunoglu, A., Derby, J., Franceschini, M., Johnson, C., Montoye, R.

“…In wireless networks, base stations are responsible for operating on large amounts of traffic at high speed rates. With the advent of new standards, as 4G,…”
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Custom is from Venus and synthesis from Mars by Puri, Ruchir, Joyner, William H, Borkar, Shekhar, Garibay, Ty, Lotz, Jonathan, Montoye, Robert

“…Due to ever increasing cost of doing design, design productivity and more specifically, cost of design has become a major bottleneck in large scale design…”
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Stable SRAM cell design for the 32 nm node and beyond by Chang, L., Fried, D.M., Hergenrother, J., Sleight, J.W., Dennard, R.H., Montoye, R.K., Sekaric, L., McNab, S.J., Topol, A.W., Adams, C.D., Guarini, K.W., Haensch, W.

“…SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for…”
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A Practical Algorithm for the Solution of Triangular Systems on a Parallel Processing System by Montoye, R K, Lawrie, D H

“…An algorithm is presented for a more efficient and implementable solution of triangular systems on a parallel (SIMD) computer which requires 0(log (N)) fewer…”
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Design of Shifting and Permutation Units using LSDL Circuit Family by Datta, R., Montoye, R., Nowka, K., Sawada, J., Abraham, J.A.

“…Migration of designs into a smaller technology node, that traditionally resulted in an increase in performance, is yielding reduced returns as we scale into…”
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Testing and debugging delay faults in dynamic circuits by Datta, R., Nassif, S., Montoye, R., Abraham, J.A.

“…We propose novel design for test and debug techniques to apply two patterns for delay fault test and debug in dynamic circuits. Dynamic circuits, which have…”
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An 8GHz floating-point multiply by Belluomini, W., Jamsek, D., Martin, A., McDowell, C., Montoye, R., Nguyen, T., Hung Ngo, Sawada, J., Vo, I., Datta, R.

“…The implementation of the mantissa portion of a floating-point multiply (54/spl times/54b) is described. The 0.124mm/sup 2/ multiplier is implemented using…”
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A Duty-Cycle Correction Circuit for High-Frequency Clocks by Agarwal, K., Montoye, R.

“…We present a circuit to control duty-cycle of high-frequency clocks with very fine resolution. The proposed duty-cycle detection and correction circuits are…”
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Demonstration of CAM and TCAM Using Phase Change Devices by Rajendran, B, Cheek, R W, Lastras, L A, Franceschini, M M, Breitwisch, M J, Schrott, A G, Jing Li, Montoye, R K, Chang, Leland, Chung Lam

“…We demonstrate novel designs for Content Addressable Memory (CAM) and Ternary CAM (TCAM) using Phase Change Memory (PCM) technology, which can potentially…”
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A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2 by Leland Chang, Montoye, R K, Ji, B L, Weger, A J, Stawiasz, K G, Dennard, R H

“…A switched-capacitor DC-DC voltage converter in 45 nm SOI CMOS leverages on-chip trench capacitors to achieve 90% efficiency at an output of 2.3A/mm 2 for 2…”
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