Search Results - "Moccio, S"

The electronic structure at the atomic scale of ultrathin gate oxides by Muller, D. A, Sorsch, T, Moccio, S, Baumann, F. H, Evans-Lutterodt, K, Timp, G

“…The narrowest feature on present-day integrated circuits is the gate oxide-the thin dielectric layer that forms the basis of field-effect device structures…”
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Quantification of scanning capacitance microscopy imaging of the pn junction through electrical simulation by O’Malley, M. L., Timp, G. L., Moccio, S. V., Garno, J. P., Kleiman, R. N.

“…Determining the cross-sectional doping profile of very small metal–oxide–semiconductor field effect transistors and specifically the direct measurement of…”
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Understanding the limits of ultrathin SiO2 and Si-O-N gate dielectrics for sub-50 nm CMOS by GREEN, M. L, SORSCH, T. W, TIMP, G. L, MULLER, D. A, WEIR, B. E, SILVERMAN, P. J, MOCCIO, S. V, KIM, Y. O

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The relentless march of the MOSFET gate oxide thickness to zero by Timp, G, Bude, J, Baumann, F, Bourdelle, K.K, Boone, T, Garno, J, Ghetti, A, Green, M, Gossmann, H, Kim, Y, Kleiman, R, Kornblit, A, Klemens, F, Moccio, S, Muller, D, Rosamilia, J, Silverman, P, Sorsch, T, Timp, W, Tennant, D, Tung, R, Weir, B

“…The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon…”
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Electrical simulation of scanning capacitance microscopy imaging of the pn junction with semiconductor probe tips by O’Malley, M. L., Timp, G. L., Timp, W., Moccio, S. V., Garno, J. P., Kleiman, R. N.

“…Scanning capacitance microscopy (SCM) enables the imaging of the two-dimensional carrier profiles of small transistors. Initial imaging utilized metal-coated…”
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Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs by Timp, G., Agarwal, A., Baumann, F.H., Boone, T., Buonanno, M., Cirelli, R., Donnelly, V., Foad, M., Grant, D., Green, M., Gossmann, H., Hillenius, S., Jackson, J., Jacobson, D., Kleiman, R., Komblit, A., Klemens, F., Lee, J.T.-C., Mansfield, W., Moccio, S., Murrell, A., O'Malley, M., Rosamilia, J., Sapjeta, J., Silverman, P., Sorsch, T., Tai, W.W., Tennant, D., Vuong, H., Weir, B.

“…Reports measurements of the DC characteristics of sub-100 nm nMOSFETs that employ low leakage ultra-thin gate oxides only 1-2 nm thick to achieve high current…”
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Progress toward 10 nm CMOS devices by Timp, G., Bourdelle, K.K., Bower, J.E., Baumann, F.H., Boone, T., Cirelli, R., Evans-Lutterodt, K., Garno, J., Ghetti, A., Gossmann, H., Green, M., Jacobson, D., Kim, Y., Kleiman, R., Klemens, F., Kornlit, A., Lochstampfor, C., Mansfield, W., Moccio, S., Muller, D.A., Ocola, I.E., O'Malley, M.I., Rosamilia, J., Sapjeta, J., Silverman, P., Sorsch, T., Tennant, D.M., Timp, W., Weir, B.E.

“…One of the primary means for improving performance and increasing the scale of integration on a chip is the miniaturization of the electronic devices that…”
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An anode hole injection percolation model for oxide breakdown-the "doom's day" scenario revisited by Alam, M.A., Bude, J., Weir, B., Silverman, P., Ghetti, A., Monroe, D., Cheung, K.P., Moccio, S.

“…A comprehensive percolation model is used to explore the role of non-uniform trap generation process on oxide breakdown. We show that this non-uniform trap…”
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Understanding the limits of ultrathin SiO sub(2) and Si-O-N gate dielectrics for sub-50 nm CMOS by Green, M L, Sorsch, T W, Timp, G L, Muller, D A, Weir, B E, Silverman, P J, Moccio, S V, Kim, Y O

“…In spite of its many attributes such as nativity to silicon, low interfacial defect density, high melting point, large energy gap, high resistivity, and good…”
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The ballistic nano-transistor by Timp, G., Bude, J., Bourdelle, K.K., Garno, J., Ghetti, A., Gossmann, H., Green, M., Forsyth, G., Kim, Y., Kleiman, R., Klemens, F., Kornblit, A., Lochstampfor, C., Mansfield, W., Moccio, S., Sorsch, T., Tennant, D.M., Timp, W., Tung, R.

“…We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (<2 nm) gate oxides in sub-30 nm effective channel…”
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Ultra-thin, 1.0-3.0 nm, gate oxides for high performance sub-100 nm technology by Sorsch, T., Timp, W., Baumann, F.H., Bogart, K.H.A., Boone, T., Donnelly, V.M., Green, M., Evans-Lutterodt, K., Kim, C.Y., Moccio, S., Rosamilia, J., Sapjeta, J., Silvermann, P., Weir, B., Timp, G.

“…We report our assessment of the limitation imposed by the tunneling current density on the scaling of stoichiometric oxides grown by rapid thermal oxidation at…”
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Ultra-thin gate oxides and ultra-shallow junctions for high performance, sub-100 nm pMOSFETs by Timp, G., Agarwal, A., Bourdella, K.K., Bower, J., Boone, T., Ghetti, A., Green, M., Gamo, J., Gossmann, H., Jacobson, D., Kleiman, R., Kornblit, A., Klemens, F., Moccio, S., O'Malley, M.L., Ocola, L., Rossm-nalia, J., Sapjeta, J., Silverman, P., Sorsch, T., Timp, W., Tennani, D.

“…Reports measurements of the DC characteristics of sub-100nm pMOSFETs that employ low leakage, ultra-thin gate oxides only 1-2nm thick and ultra-shallow…”
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