Search Results - "Miyano, Kiyotaka"

SOI/Bulk Hybrid Wafer Fabrication Process Using Selective Epitaxial Growth (SEG) Technique for High-End SoC Applications by Nagano, Hajime, Sato, Tsutomu, Miyano, Kiyotaka, Yamada, Takashi, Mizushima, Ichiro

“…The size of SiN region and the growth condition were investigated for the robust process of selective epitaxial growth for the fabrication of the Si on…”
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Defects Induced by Carbon Contamination in Low-Temperature Epitaxial Silicon Films Grown with Monosilane by Sato, Shin'ya, Mizushima, Ichiro, Miyano, Kiyotaka, Sato, Tsutomu, Nakamura, Shin'ichi, Tsunashima, Yoshitaka, Arikado, Tsunetoshi, Uchitomi, Naotaka

“…The structures of the defects induced by carbon contamination in epitaxial silicon films grown with monosilane (SiH 4 ) on silicon substrates were…”
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Oxide-Mediated Solid Phase Epitaxy (OMSPE) of Silicon: A New Low-Temperature Epitaxy Technique Using Intentionally Grown Native Oxide by Mizushima, Ichiro, Mitani, Yuichiro, Miyano, Kiyotaka, Kambayashi, Shigeru

“…A new low-temperature epitaxial technique is proposed, which utilizes the native oxide on the Si surface. A good quality epitaxial Si layer can be obtained…”
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Influence of Reactive Ion Etching Applied to Si Substrate on Epitaxial Si Growth and Its Removal by Hayashi, Hisataka, Ohuchi, Kazuya, Miyano, Kiyotaka, Hokazono, Akira, Mizushima, Ichiro, Ohiwa, Tokuhisa

“…The effects of post-etching treatments on Si selective epitaxial growth (SEG) have been studied. In the case of O 2 downflow treatment, SEG Si had dislocations…”
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Reduction in number of crystal defects in a p^sup +^Si diffusion layer by germanium and boron cryogenic implantation combined with sub-melt laser spike annealing by Murakoshi, Atsushi, Harada, Tsubasa, Miyano, Kiyotaka, Harakawa, Hideaki, Aoyama, Tomonori, Yamashita, Hirofumi, Kohyama, Yusuke

“…To reduce the number of crystal defects in a p+Si diffusion layer by a low-thermal-budget annealing process, we have examined crystal recovery in the amorphous…”
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Reduction in number of crystal defects in a p+Si diffusion layer by germanium and boron cryogenic implantation combined with sub-melt laser spike annealing by Murakoshi, Atsushi, Harada, Tsubasa, Miyano, Kiyotaka, Harakawa, Hideaki, Aoyama, Tomonori, Yamashita, Hirofumi, Kohyama, Yusuke

“…To reduce the number of crystal defects in a p+Si diffusion layer by a low-thermal-budget annealing process, we have examined crystal recovery in the amorphous…”
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Origin and suppression of critical deep pit in high-electron-mobility transistor structure using GaN on Si technology with strained-layer superlattice by Miyano, Kiyotaka, Tsukui, Masayuki, Nago, Hajime, Iyechika, Yasushi, Kobayashi, Takehiko, Ishikawa, Yoshitaka, Takahashi, Hideshi, Mitani, Shinichi, Yoda, Takashi

“…For the utilization of high-electron-mobility transistor (HEMT) devices fabricated on GaN on Si structure as high-power devices, deep pits, which are known as…”
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Facet-Free Si Selective Epitaxial Growth Adaptable to Elevated Source/Drain MOSFETs with Narrow Shallow Trench Isolation by Miyano, Kiyotaka, Mizushima, Ichiro, Hokazono, KazuyaOhuchi, Tsunashima, Yoshitaka

“…A novel selective epitaxial growth (SEG) process that realizes a facet-free elevated source/drain (S/D) is proposed. The key points are the appropriate…”
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Boron diffusion layer formation using Ge cryogenic implantation with low-temperature microwave annealing by Murakoshi, Atsushi, Harada, Tsubasa, Miyano, Kiyotaka, Harakawa, Hideaki, Aoyama, Tomonori, Yamashita, Hirofumi, Kohyama, Yusuke

“…It is shown that a low-sheet-resistance p-type diffusion layer with a small diffusion depth can be fabricated efficiently by cryogenic boron and germanium…”
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Mechanism of Defect Formation during Low-Temperature Si Epitaxy on Clean Si Substrate by Mizushima, Ichiro, Koike, Mitsuo, Sato, Tsutomu, Miyano, Kiyotaka, Tsunashima, Yoshitaka

“…Defects having a mound structure are formed during Si epitaxy on (001) Si substrates by low-pressure chemical vapor deposition at a low temperature of 700°C…”
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Carbon Incorporation into Substitutional Silicon Site by Molecular Carbon Ion Implantation and Recrystallization Annealing as Stress Technique in n-Metal--Oxide--Semiconductor Field-Effect Transistor by Itokawa, Hiroshi, Miyano, Kiyotaka, Oshima, Yasunori, Mizushima, Ichiro, Suguro, Kyoichi

“…Since the lattice constant of silicon-carbon (Si:C) is smaller than that of Si, Si:C embedded in the source and drain (e-Si:C S/D) can induce tensile stress in…”
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A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32 nm node high-performance pMOSFET technology by Okamoto, Hiroki, Yasutake, Nobuaki, Kusunoki, Naoki, Adachi, Kanna, Itokawa, Hiroshi, Miyano, Kiyotaka, Ishida, Tatsuya, Hokazono, Akira, Kawanaka, Shigeru, Mizushima, Ichiro, Azuma, Atsushi, Toyoshima, Yoshiaki

“…In general, closer proximity of embedded SiGe (eSiGe) source drain (S/D) structure to the channel improves p-channel metal oxide semiconductor field-effect…”
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A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32nm node high-performance pMOSFET technology by Okamoto, Hiroki, Yasutake, Nobuaki, Kusunoki, Naoki, Adachi, Kanna, Itokawa, Hiroshi, Miyano, Kiyotaka, Ishida, Tatsuya, Hokazono, Akira, Kawanaka, Shigeru, Mizushima, Ichiro, Azuma, Atsushi, Toyoshima, Yoshiaki

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Multi-wavelength Reflectivity Monitoring on Growth of AlN on Si by Iyechika, Yasushi, Tsukui, Masayuki, Miyano, Kiyotaka, Takahashi, Hideshi

“…Analysis of oscillation of reflectivity on thin film growth at a wavelength the film is transparent results in more than one solution of growth rate sometimes…”
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Robustness of a selective epitaxial-growth process of silicon and its application to the fabrication of a high-quality hybrid SOI wafer : Materials-related manufacturing issues in the nanochip era by NAGANO, Hajime, MIYANO, Kiyotaka, YAMADA, Takashi, MIZUSHIMA, Ichiro

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Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology by Inaba, S., Nagano, H., Miyano, K., Mizushima, I., Okayama, Y., Nakauchi, T., Ishimaru, K., Ishiuchi, H.

“…In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) is investigated with a view to realizing high-speed and low-power CMOS…”
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Robustness of a selective epitaxial-growth process of silicon and its application to the fabrication of a high-quality hybrid SOI wafer by Nagano, H., Miyano, K., Yamada, T., Mizushima, I.

“…Robustness of a selective epitaxial growth of silicon is demonstrated. The process window of selectivity was estimated quantitatively using the Taguchi method…”
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SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology by Inaba, S., Miyano, K., Nagano, H., Hokazono, A., Ohuchi, K., Mizushima, I., Oyamatsu, H., Tsunashima, Y., Ishimaru, K., Toyoshima, Y., Ishiuchi, H.

“…In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the…”
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Highly Uniform Low-Pressure Chemical Vapor Deposition (LP-CVD) of Si 3 N 4 Film on Tungsten for Advanced Low-Resistivity “Polymetal” Gate Interconnects by Akasaka, Yasushi, Miyano, Kiyotaka, Takahashi, KazuakiNakajima, Tanaka, Satoko, Suguro, Kyoichi

“…A W/WSiN/poly-Si multilayered “polymetal” gate structure has been proposed. An extremely low sheet resistivity can be achieved with this structure (1.4 Ω/□: T…”
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Low-resistivity poly-metal gate electrode durable for high-temperature processing by Akasaka, Y., Suehiro, S., Nakajima, K., Nakasugi, T., Miyano, K., Kasai, K., Oyamatsu, H., Kinugawa, M., Takagi, M.T., Agawa, K., Matsuoka, F., Kakumu, M., Suguro, K.

“…A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100…”
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