Search Results - "Minoret, Stephane"
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Development of Ni₂P Contact Technology and Its Integration on III-V Materials for 300 mm Si Photonics Platform
Published in IEEE journal of the Electron Devices Society (2022)“…In order to assess their potential use as contact layers for Si photonics devices, Ni 2 P thin films were developed on a 300 mm platform. The Ni 2 P layers,…”
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Journal Article -
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Study of low temperature MOCVD deposition of TiN barrier layer for copper diffusion in high aspect ratio through silicon vias
Published in Microelectronic engineering (25-05-2014)“…•The MOCVD TiN films are N-riched.•Plasma treatment changes the films from amorphous to 7nm crystal grain size.•The films have larger gap in Ti and N…”
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Journal Article Conference Proceeding -
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Ultra Wide Micro Bumps Interconnection Matrix for High Energy Particle Detection: Process and Assembly
Published in 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) (01-05-2019)“…Micro pillars and micro bumps interconnections are considered as mature technology for 3-D integration and chip stacking. However, in the framework of…”
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Conference Proceeding -
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Through silicon via process characterization by integrated inspection/metrology solutions in visible and infrared domain
Published in 2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) (01-05-2015)“…In this paper, we present an integrated in-line solution, combining automatic visual inspection/classification with unique 2D/3D measurement technologies,…”
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Conference Proceeding -
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Advanced Metallizatisn Processes Integration as Manufacturing Worthy Solutions for > 10:1 Aspect Ratio Mid-Process TSV
Published in 2018 IEEE International Interconnect Technology Conference (IITC) (01-06-2018)“…For many years, TSV has become a key technology driver for 3D integration of heterogeneous devices. Among the different ways to create TSV, mid-process…”
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Conference Proceeding -
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Silicon embedded line integration for high end passive silicon interposer
Published in 2013 Eurpoean Microelectronics Packaging Conference (EMPC) (01-09-2013)“…As standard organic substrate packages and wire bonding are reaching their limits in term of wiring density and integration capacity, silicon interposer…”
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Conference Proceeding -
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Electrical and morphological characterization for high integrated silicon interposer and technology transfer from 200 mm to 300mm wafer
Published in 2013 IEEE 63rd Electronic Components and Technology Conference (01-05-2013)“…To achieve high density and high speed transmission between chips, a silicon interposer with copper (Cu) Through Silicon Vias (TSVs) technologies have been…”
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Conference Proceeding -
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6.6W/mm 200mm CMOS compatible AlN/GaN/Si MIS-HEMT with in-situ SiN gate dielectric and low temperature ohmic contacts
Published in 2023 International Electron Devices Meeting (IEDM) (09-12-2023)“…We report on the development of CMOS compatible SiN/AlN/GaN MIS-HEMT process on 200mm Si substrates for Ka-band power amplification. The combination of soft…”
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Conference Proceeding