A simple EEPROM cell using twin polysilicon thin film transistors

A simple EEPROM cell using twin polysilicon thin film transistors

A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (/spl les/600/spl deg/C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the la...

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Bibliographic Details
Published in:IEEE electron device letters Vol. 15; no. 8; pp. 304 - 306
Main Authors: Mino Cao, Tiemin Zhao, Saraswat, K.C., Plummer, J.D.
Format: Journal Article
Language:English
Published: New York, NY IEEE 01-08-1994
Institute of Electrical and Electronics Engineers
Subjects:
Active matrix liquid crystal displays
Annealing
Applied sciences
Capacitance
Costs
Design. Technologies. Operation analysis. Testing
Electrodes
Electronics
EPROM
Exact sciences and technology
Integrated circuits
Nonvolatile memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Temperature
Thin film transistors
Tunneling
EEPROM memory
Integrated circuit
Polycrystal
Silicon
Thin film transistor
Experimental study
Electrical characteristic
Planar technology
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Summary:A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (/spl les/600/spl deg/C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0741-3106
1558-0563
DOI:10.1109/55.296224