Search Results - "Min-Jer Wang"

A Local Parallel Search Approach for Memory Failure Pattern Identification by Bing-Yang Lin, Cheng-Wen Wu, Lee, Mincent, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

“…Due to more aggressive design rules adopted by memories than logic circuits, memories have been considered as the major technology driver of advanced logic…”
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A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application by Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Adham, Saman, Min-Jer Wang, Shen, William Wu, Mehta, Ashok

“…A 1 Tbit/s bandwidth PHY is demonstrated through CoWoS™ platform. Two chips: SOC and embedded DRAM (eDRAM), have been fabricated in TSMC 40 nm CMOS technology…”
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Fan-out wafer level chip scale package testing by Hao Chen, Hung-Chih Lin, Min-Jer Wang

“…This paper introduces test solutions for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promising of being a very cost…”
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3D-IC interconnect test, diagnosis, and repair by Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin

“…Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and…”
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Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study by Goel, Sandeep Kumar, Adham, Saman, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Mehta, Ashok, Lee, Frank, Chickermane, Vivek, Keller, Brion, Valind, Thomas, Mukherjee, Subhasish, Sood, Navdeep, Jeongho Cho, Lee, Hayden Hyungdong, Jungi Choi, Sangdoo Kim

“…Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration…”
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Testing-for-manufacturing (TFM) for ultra-thin IPD on InFO by Tang-Jung Chiu, Yu-Lun Tseng, Yen-Cheng Lin, Yi-Chen Wang, Hung-Chih Lin, Min-Jer Wang

“…The Integrated Fan Out (InFO) technology can accom-plish package miniaturization and successfully achieve "More than Moore's Law." Its substrate-free…”
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Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package by Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

“…With the increasing demand of super high scale of integration and small form factor in advanced semiconductor products, especially those that integrate DRAM…”
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Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology by Hsieh, Henry, Dhong, Sang H., Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang

“…We describe custom 6R, 2/4W general-purpose register files (GRF) in an ASIC-based SOC implemented in a N28 CMOS technology, which has roughly a 2~3 X smaller…”
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Wafer Level Chip Scale Package copper pillar probing by Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

“…This paper introduces a probing methodology for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promise of being a very cost…”
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A memory yield improvement scheme combining built-in self-repair and error correction codes by Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang

“…Error correction code (ECC) and built-in self-repair (BISR) schemes have been wildly used for improving the yield and reliability of memories. Many built-in…”
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Redundancy architectures for channel-based 3D DRAM yield improvement by Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Lee, Mincent, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

“…The three-dimensional integrated circuit (3D IC) is considered a promising approach that can obtain high data band-width and low power consumption for future…”
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A 4-GHz universal high-frequency on-chip testing platform for IP validation by Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang

“…This paper describes an on-chip intellectual property (IP) testing platform, Universal High Frequency Test structure (UHFTs), which makes logic, memory, and…”
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Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch by Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

“…High-density probing is a main trend of the test technology. The warping issues of probe card are caused by the high-density test. The metal backer and patches…”
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High Quality Test Methodology for Highly Reliable Devices by Chen, Hao, Lee, Mincent, Chen, Liang-Yen, Wang, Min-Jer

“…This paper introduces a high quality screening methodology, using Integrated Passive Device (IPD) as an example device, which has the capability to increase…”
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A Built-Off Self-Repair Scheme for Channel-Based 3D Memories by Liu, Hsuan-Hung, Lin, Bing-Yang, Wu, Cheng-Wen, Chiang, Wan-Ting, Mincent, Lee, Lin, Hung-Chih, Peng, Ching-Nen, Wang, Min-Jer

“…Redundancy repair is a commonly used technique for memory yield improvement. In order to ensure high repair rate and final product yield, it is necessary to…”
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A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices by Chuang, Chien-Hui, Hou, Kuan-Wei, Wu, Cheng-Wen, Lee, Mincent, Tsai, Chia-Heng, Chen, Hao, Wang, Min-Jer

“…Integrated passive devices (IPDs) have been widely used in advanced packaging of semiconductor chips, to improve their power integrity and impedance matching…”
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Heterogeneous Power Delivery for 7nm High-Performance Chiplet-Based Processors using Integrated Passive Device and In-Package Voltage Regulator by Roth, Alan, Zhou, Charlie, Wong, Mei, Soenen, Eric, Huang, Tze-Chiang, Ranucci, Paul, Hsu, Ying-Chih, Lin, Hung-Chih, Kuo, Chester, Wang, Min-Jer, Yang, Sheng-Yao, Chu, J. R., Yeh, Ting-Yu, Ting, K. C., Loke, Alvin L. S., Rusu, Stefan, Chen, Mark, Lee, Frank Y. H., Zhang, Kevin, Kalnitsky, Alex

“…We demonstrate two heterogeneous solutions to improve power delivery to High-Performance Computing (HPC) processors. The scalable HPC vehicle integrates two…”
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A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC by Sang Dhong, Guo, Richard, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang

“…We present a pulse latch with a measured Vccmin at the circuit of 0.42 V and pulse width of approximately 3 FO4-inverter delays. A wider operating window and…”
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Novel adaptive probing for wafer level chip scale package by Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

“…To be "More than Moore's law", Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is more cost-effective than other 3D-integrated-circuit (3DIC)…”
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A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS by Ming-Zhang Kuo, Hsieh, Henry, Sang Dhong, Ping-Lin Yang, Cheng-Chung Lin, Tseng, Ryan, Kevin Huang, Min-Jer Wang, Wei Hwang

“…This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V…”
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