Search Results - "Millican, Spencer"

Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion by Sun, Yang, Millican, Spencer K.

“…This study applies artificial neural networks (ANNs) to increase stuck-at and delay fault coverage of logic built-in self-test (LBIST) through test point…”
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A Survey and Recent Advances: Machine Intelligence in Electronic Testing by Roy, Soham, Millican, Spencer K., Agrawal, Vishwani D.

“…Integrated circuit (IC) testing presents complex problems that for large circuits are exceptionally difficult to solve by traditional computing techniques. To…”
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Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits by Roy, Soham, Millican, Spencer K., Agrawal, Vishwani D.

“…Integrated circuit (IC) testing presents complex problems that, when ICs become large, are exceptionally difficult to solve by traditional computing…”
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Machine Intelligence for Efficient Test Pattern Generation by Roy, Soham, Millican, Spencer K., Agrawal, Vishwani D.

“…This study examines machine intelligence's (MI) ability to enhance automatic test pattern generation (ATPG) by reducing backtracks. In lieu of a conventional…”
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Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator by Roy, Soham, Millican, Spencer K., Agrawal, Vishwani D.

“…Recent research shows that an artificial neural network (ANN) can combine multiple heuristics to guide an automatic test pattern generator (ATPG) with fewer…”
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Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training by Millican, Spencer, Sun, Yang, Roy, Soham, Agrawal, Vishwani

“…This article presents methods of increasing logic built-in self-test (LBIST) delay fault coverage using artificial neural networks (ANNs) to selecting test…”
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Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures by Roy, Soham, Stiene, Brandon, Millican, Spencer K., Agrawal, Vishwani D.

“…This article analyzes and rationalizes the capabilities of inversion test points (TPs) when implemented in lieu of traditional test point architectures. With…”
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Special Session: Survey of Test Point Insertion for Logic Built-in Self-test by Sun, Yang, Millican, Spencer K., Agrawal, Vishwani D.

“…This article surveys test point (TP) architectures and test point insertion (TPI) methods for increasing pseudo-random and logic built-in self-test (LBIST)…”
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Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling by Millican, Spencer K., Saluja, Kewal K.

“…As a consequence of technology scaling and increasing power consumption of modern high performance designs, various techniques, such as clock gating and…”
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A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits by Millican, Spencer K., Saluja, Kewal K.

“…Increasing design complexity coupled with new design and manufacturing techniques being used for modern integrate circuits is creating challenges for test…”
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Test Point Insertion Using Artificial Neural Networks by Sun, Yang, Millican, Spencer

“…A method of data collecting, training, and using artificial neural networks (ANNs) for evaluating test point (TP) quality for TP insertion (TPI) is presented…”
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Multi-Heuristic Machine Intelligence Guidance in Automatic Test Pattern Generation by Roy, Soham, Millican, Spencer K., Agrawal, Vishwani D.

“…We present an automatic test pattern generation (ATPG) system using the PODEM (path-oriented decision making) algorithm where backtraces and D-drive are…”
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Calculating Signal Controllability using Neural Networks: Improvements to Testability Analysis and Test Point Insertion by Immanuel, Joshua, Millican, Spencer K.

“…This article presents an artificial neural network-based signal probability predictor for VLSI circuits which considers reconvergent fan-outs. Current…”
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Unsupervised Learning in Test Generation for Digital Integrated Circuits by Roy, Soham, Millican, Spencer K., Agrawal, Vishwani D.

“…The exponential complexity of automatic test pattern generation (ATPG) necessitates the use of heuristics in making choices during test generation. However, in…”
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Principal Component Analysis in Machine Intelligence-Based Test Generation by Roy, Soham, Millican, Spencer K., Agrawal, Vishwani D.

“…In a machine intelligence (MI)-based automatic test pattern generator (ATPG), an artificial neural network (ANN) may guide decisions that would otherwise rely…”
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Special Session: Delay Fault Testing - Present and Future by Mahmod, Jubayer, Millican, Spencer, Guin, Ujjwal, Agrawal, Vishwani

“…This article presents a brief survey of digital delay fault testing, which lists 100+ references on fault models, simulators, ATPG, DFT, and tools. Continuing…”
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A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories by Fadamiro, Ayokunle, Rezaie, Pouyan, Millican, Spencer, Harris, Christoper B.

“…Consumer demands are outgrowing the benefits of technology scaling, especially for binary circuits. Previous studies proposed multi-valued logic (MVL)…”
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CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities by Millican, Spencer, Ramanathan, Parameswaran, Saluja, Kewal

“…Modern complex digital designs are becoming feasible due to the use of System on Chip design techniques in which designers use Intellectual Property (IP) cores…”
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Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints by Millican, Spencer K., Saluja, Kewal K.

“…As Integrated Circuits (ICs) become more complex through smaller semiconductor feature sizes and higher performance requirements, the thorough testing of…”
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Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling by Millican, Spencer K., Saluja, Kewal K.

“…Various techniques for modern high performance designs, such as clock gating and dynamic voltage frequency scaling (DVFS), have been adapted to address power…”
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