Search Results - "Miéville, P"

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  1. 1

    Hyperpolarizing gases via dynamic nuclear polarization and sublimation by Comment, A, Jannin, S, Hyacinthe, J-N, Miéville, P, Sarkar, R, Ahuja, P, Vasos, P R, Montet, X, Lazeyras, F, Vallée, J-P, Hautle, P, Konter, J A, van den Brandt, B, Ansermet, J-Ph, Gruetter, R, Bodenhausen, G

    Published in Physical review letters (02-07-2010)
    “…A high throughput method was designed to produce hyperpolarized gases by combining low-temperature dynamic nuclear polarization with a sublimation procedure…”
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    Journal Article
  2. 2
  3. 3

    Relaxometry of insensitive nuclei: Optimizing dissolution dynamic nuclear polarization by Miéville, Pascal, Jannin, Sami, Bodenhausen, Geoffrey

    Published in Journal of magnetic resonance (1997) (01-05-2011)
    “…The scheme shows a dissolution-DNP polarizer and a 800 MHz NMR magnet. The hyperpolarized sample experiences very low fields during its transfer, which…”
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    Journal Article
  4. 4

    Effect of electron heating on electron capture cross section in very small metal-oxide-semiconductor transistors by SHI, Z. M, MIEVILLE, J.-P, DUTOIT, M

    Published in Applied physics letters (03-05-1993)
    “…The effect of electron heating on random telegraph signals due to oxide traps in deep-submicron n-channel MOSFETs is shown. A simple theoretical model gives a…”
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    Journal Article
  5. 5

    Random telegraph signals in deep submicron n-MOSFET's by Zhongming Shi, Mieville, J.-P., Dutoit, M.

    Published in IEEE transactions on electron devices (01-07-1994)
    “…Random telegraph signals (RTS) in the drain current of deep-submicron n-MOSFET's are investigated at low and high lateral electric fields. RTS are explained…”
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    Journal Article
  6. 6

    Low Frequency Noise in 100 nm n-MOSFET's at Low Temperatures by Shi, Z. M., Mieville, J.-P., Barrier, J., Dutoit, M.

    “…This work shows that charge trapping and detrapping in the gate oxide, which produce low-frequency noise in the drain current of MOSFET's in the classical…”
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    Conference Proceeding
  7. 7

    Effect of electron heating on RTS in deep submicron n-MOSFET's by Shi, Z.M., Mieville, J.P., Dutoit, M.

    “…The influence of electron heating due to the lateral electric field on RTS in deep submicrometer MOSFET's is analyzed. The mean capture time by acceptor traps…”
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    Conference Proceeding
  8. 8

    Electron heating and quantum transport in deep submicrometer n-MOSFET's at low temperatures and high magnetic fields by Mieville, J.P., Ouisse, T., Cristoloveanu, S., Revil, N., Shi, Z.M., Dutoit, M.

    “…We studied Shubnikov-de Haas oscillations in Si MOSFET's with gate lengths ranging from 0.1 μm to 2 μm. They show a reduction of electron temperature for a…”
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    Conference Proceeding
  9. 9

    Performance and reliability aspects of FOND: a new deep submicron CMOS device concept by Bellens, R., Van den Bosch, G., Habas, P., Mieville, J.-P., Badenes, G., Clerix, A., Groeseneken, G., Deferm, L., Maes, H.E.

    Published in IEEE transactions on electron devices (01-09-1996)
    “…The electrical performance and the hot-carrier degradation behavior of a new type of fully overlapped device called FOND (Fully Overlapped Nitride-etch defined…”
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    Journal Article
  10. 10

    Quantum Transport Effects in Deep Submicron n-MOSFET by Mieville, J.P., Eschle, M., Shi, Z.M., Barrier, J., Dutoit, M., Moret, J.M., Oppliger, Y.

    “…MOSFET's with gate lengths down to 0.1 μm were characterized at low temperatures. Below 20 K, characteristic peaks in the transconductance were observed in…”
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    Conference Proceeding
  11. 11

    FOND (Fully Overlapped Nitride-etch defined Device): a new device architecture for high-reliability and high-performance deep submicron CMOS technology by Mieville, J.-P., Van den Bosch, G., Deferm, L., Bellens, R., Groeseneken, G., Maes, H.E., Schoenmaker, W.

    “…An alternative device architecture for improved hot carrier reliability which is based on the GOLD concept is proposed. The gate overlap is accurately…”
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    Conference Proceeding Journal Article
  12. 12

    An Optimized Poly-Buffered LOCOS Process for a 0.35 μm CMOS Technology by Mieville, J.-P., Rooyackers, R., Deferm, L.

    “…For a 0.35 μm CMOS technology, an optimized poly buffered LOCOS process is necessary in order to meet the design rules. In this paper, the feasibility of this…”
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    Conference Proceeding
  13. 13

    Study of the hot-carrier degradation performance of 0.35-μm fully overlapped LDD devices by Bellens, R., Habaš, P., Groeseneken, G., Maes, H.E., Miéville, J.P., Van den bosch, G., Deferm, L.

    Published in Microelectronic engineering (01-06-1995)
    “…The hot-carrier performance of a new type of fully overlapped device (FOND) is analysed and compared to the degradation behaviour of conventional LDD devices…”
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    Journal Article
  14. 14

    Low frequency noise and quantum transport in 0.1 mu m n-MOSFETs by Shi, Z.M., Mieville, J.-P., Barrier, J., Dutoit, M.

    “…Random telegraph signals (RTS) produced in deep-submicron n-MOSFETs by single electron capture and emission on oxide traps ar studied. Trap parameters, energy…”
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    Conference Proceeding