Search Results - "Mergens, M.P.J."

Analysis of lateral DMOS power devices under ESD stress conditions by Mergens, M.P.J., Wilkening, W., Mettler, S., Wolf, H., Stricker, A., Fichtner, W.

“…The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission line…”
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Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies by Mergens, M.P.J., Russ, C.C., Verhaege, K.G., Armer, J., Jozwiak, P.C., Mohn, R.P., Keppens, B., Trinh, C.S.

“…A novel diode-triggered silicon-controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for…”
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Advanced SCR ESD protection circuits for CMOS/SOI nanotechnologies by Mergens, M.P.J., Marichal, O., Thijs, S., Van Camp, B., Russ, C.C.

“…This paper reviews the application of SCR-based ESD protection circuits in advanced CMOS/SOI technologies. The devices are integrated in a flexible modular…”
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ESD protection considerations in advanced high-voltage technologies for automotive by Mergens, M.P.J., Mayerhofer, M.T., Willemen, J.A., Stecher, M.

“…This paper discusses challenges and solutions of automotive ESD protection design in a reliability driven industry. Various ESD/EMI specifications are…”
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ESD protection solutions for high voltage technologies by Keppens, B., Mergens, M.P.J., Cong Son Trinh, Russ, C.C., Van Camp, B., Verhaege, K.G.

“…There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD…”
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Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides by Mergens, M.P.J., Russ, C.C., Verhaege, K.G., Armer, J., Jozwiak, P.C., Mohn, R., Keppens, B., Trinh, C.S.

“…A novel diode-triggered SCR (DTSCR) ESD protection element is introduced for low-voltage application (signal, supply voltage /spl les/1.8 V) and extremely…”
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Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling by Mergens, M.P.J., Verhaege, K.G., Russ, C.C., Armer, J., Jozwiak, P.C., Kolluri, G., Avery, L.R.

“…A silicon-proven multi-finger turn-on (MFT) design technique that enables ESD width scaling combined with very low dynamic on-resistance is presented in…”
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GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes by Russ, C.C., Mergens, M.P.J., Verhaege, K.G., Armer, J., Jozwiak, P.C., Kolluri, G., Avery, L.R.

“…In this paper, design aspects, operation, protection capability and applications of SCRs in deep sub-micron CMOS are addressed. A novel Grounded-Gate NMOS…”
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Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design by Keppens, B., Mergens, M.P.J., Armer, J., Jozwiak, P.C., Taylor, G., Mohn, R., Cong Son Trinh, Russ, C.C., Verhaege, K.G., De Ranter, F.

“…This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and…”
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ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior by Mergens, M.P.J., Wilkening, W., Kiesewetter, G., Mettler, S., Wolf, H., Hieber, J., Fichtner, W.

“…An extraction method for the effective gate RC-delay of MOS single- and multi-finger structures is introduced by deducing a rule of thumb for the effective…”
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Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies by Mergens, M.P.J., Russ, C.C., Verhaege, K.G., Armer, J., Jozwiak, P.C., Mohn, R.P., Keppens, B., Trinh, C.S.

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