Search Results - "Mercer, M.R."

Defect-oriented testing and defective-part-level prediction by Dworak, J., Wicker, J.D., Lee, S., Grimaila, M.R., Mercer, M.R., Butler, K.M., Stewart, B., Wang, L.-C.

“…After an integrated circuit (IC) design is complete, but before first silicon arrives from the manufacturing facility, the design team prepares a set of test…”
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Multi-level logic minimization through fault dictionary analysis by Mehler, R.W., Mercer, M.R.

“…Presents the results of the study of a new algorithm for multi-level logic minimization. The study is based on the premise that an untestable node is a…”
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An optimal test pattern selection method to improve the defect coverage by Yuxin Tian, Grimaila, M.R., Weiping Shi, Mercer, M.R.

“…It is well known that n-detection test sets are effective to detect unmodeled defects and improve the defect coverage. However, in these sets, each of the…”
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REDO-random excitation and deterministic observation-first commercial experiment by Grimaila, M.R., Sooryong Lee, Dworak, J., Butler, K.M., Stewart, B., Balachandran, H., Houchins, B., Mathur, V., Jaehong Park, Wang, L.-C., Mercer, M.R.

“…For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective…”
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Balanced excitation and its effect on the fortuitous detection of dynamic defects by Dworak, J., Cobb, B., Wingfield, J., Mercer, M.R.

“…Dynamic defects are less likely to be fortuitously detected than static defects because they have more stringent detection requirements. We show that (in…”
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A new ATPG algorithm to limit test set size and achieve multiple detections of all faults by Sooryong Lee, Cobb, B., Dworak, J., Grimaila, M.R., Mercer, M.R.

“…Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple…”
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Excitation, observation, and ELF-MD: optimization criteria for high quality test sets by Dworak, J., Dorsey, D., Wang, A., Mercer, M.R.

“…In previous work, we have shown that optimizing the number of site observations leads to more defect detection. However, for increasingly difficult defects,…”
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Iddq test: sensitivity analysis of scaling by Williams, T.W., Dennard, R.H., Kapur, R., Mercer, M.R., Maly, M.

“…While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the…”
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Function-based dynamic compaction and its impact on test set sizes by Wingfield, J., Dworak, J., Mercer, M.R.

“…Due to the limited amount of available resources and time used for manufacture testing of integrated circuits, there is great interest in minimizing the number…”
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Code coverage, what does it mean in terms of quality? by Williams, T.W., Mercer, M.R., Mucha, J.P., Kapur, R.

“…Unit code test coverage has long been known to be an important metric for testing software, and many development groups require 85% coverage to achieve quality…”
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A preliminary investigation of observation diversity for enhancing fortuitous detection of defects by Dworak, J., Wingfield, J., Mercer, M.R.

“…Unmodeled defects must be fortuitously detected by test pattern sets to achieve low defective part levels. However, fortuitous detection of many complex…”
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Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D by Dworak, J., Grimaila, M.R., Sooryong Lee, Wang, L.-C., Mercer, M.R.

“…Predicting the final value of the defective part level after the application of a set of test vectors is not a simple problem. In order for the defective part…”
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The influences of fault type and topology on fault model performance and the implications to test and testable design by Butler, K.M., Mercer, M.R.

“…A new method, difference propagation, is proposed to analyze fault models in combinational circuits. It propagates Boolean functional information represented…”
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An efficient delay test generation system for combinational logic circuits by Park, E.S., Mercer, M.R.

“…An efficient delay test generation system for combinational logic circuits is presented. Delay testing problems are divided into gross-delay fault testing and…”
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Efficient logic-level timing analysis using constraint-guided critical path search by Chanhee Oh, Mercer, M.R.

“…As the operating speed of digital circuits dramatically increases with the advance of VLSI technology, it is becoming more critical to ensure that the circuits…”
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Directed-binary search in logic BIST diagnostics by Kapur, R., Williams, T.W., Mercer, M.R.

“…Logic BIST is about to become a more main stream test method for IC testing. In some flows when a failure is encountered the IC is diagnosed to determine the…”
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A method of delay fault test generation by Glover, C.T., Mercer, M.R.

“…The authors propose an efficient deterministic method of delay fault test generation. For most common circuits, the proposed technique has a time complexity…”
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A topological search algorithm for ATPG by Kirkland, T., Mercer, M. R.

“…The automatic generation of tests for combinational digital circuits is examined from the standpoint of a guided search through a search space. The limitations…”
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An efficient delay test generation system for combinational logic circuits by Eun Sei Park, Mercer, M.R.

“…An efficient delay test generation (DTEST GEN) system for combinational logic circuits is presented. In the DTEST GEN system, delay testing problems are…”
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Fortuitous detection and its impact on test set sizes using stuck-at and transition faults by Dworak, J., Wingfield, J., Cobb, B., Sooryong Lee, Wang, L.-C., Mercer, M.R.

“…During manufacture testing, the maximum number of test patterns that can be applied is limited by the available amount of tester memory. This paper…”
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