Search Results - "Merakos, P"

Wide-band substrate crosstalk sensor for wireless SoC applications by Noulis, T., Merakos, P., Lourandakis, E., Stefanou, S., Moisiadis, Y.

“…•Substrate crosstalk sensing was performed in a 65nm CMOS ZigBee wireless communication SoC, using a novel CMOS differential architecture.•The proposed noise…”
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A single-chip digitally calibrated 5.15~5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN by Vassiliou, I., Vavelidis, K., Georgantas, T., Plevridis, S., Haralabidis, N., Kamoulakos, G., Kapnistis, C., Kavadias, S., Kokolakis, Y., Merakos, P., Rudell, J.C., Yamanaka, A., Bouras, S., Bouras, I.

“…The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz…”
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Memory accesses reordering for interconnect power reduction in sum-of-products computations by Masselos, K., Theoharis, S., Merakos, P., Stouraitis, T., Goutis, C.E.

“…Techniques for interconnect power consumption reduction in realizations of sum-of-products computations are presented. The proposed techniques reorder the…”
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Power efficient data path synthesis of sum-of-products computations by Masselos, K., Merakos, P., Theoharis, S., Stouraitis, T., Goutis, C.E.

“…Techniques for the power efficient data path synthesis of sum-of-products computations between data and coefficients are presented. The proposed techniques…”
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Novel techniques for bus power consumption reduction in realizations of sum-of-product computation by Masselos, K., Merakos, P., Stouraitis, T., Goutis, C.E.

“…Novel techniques for power-efficient implementation of sum of product computation are presented. The proposed techniques aim at reducing the switching activity…”
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A novel algorithm for low-power image and video coding by Masselos, K., Merakos, P., Stouraitis, T., Goutis, C.E.

“…A novel scheme for low-power image and video coding and decoding is presented. It is based on vector quantization, and reduces its memory requirements, which…”
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Low power architectures for digital signal processing by Masselos, K., Merakos, P., Stouraitis, T., Goutis, C.E.

“…Low power architectures for digital signal processing algorithms requiring inner product computation are presented. In the first step a power efficient memory…”
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A power grid analysis and verification tool based on a Statistical Prediction Engine by Tsiampas, M K, Bountas, D, Merakos, P, Evmorfopoulos, N E, Bantas, S, Stamoulis, G I

“…Voltage drops are one of the most stringent problems in modern IC implementation, which is exacerbated by the ever decreasing transistor sizes and interconnect…”
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Low power synthesis of sum-of-products computation (poster session) by Masselos, K., Theoharis, S., Merakos, P. K., Stouraitis, T., Goutis, C. E.

“…Novel techniques for the power efficient synthesis of sum-of-product computations are presented. Simple and efficient heuristics for scheduling and assignment…”
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Novel vector quantization based algorithms for low-power image coding and decoding by Masselos, K., Merakos, P., Stouraitis, T., Goutis, C.E.

“…In this paper, a novel scheme for low-power image coding and decoding based on vector quantization is presented. The proposed scheme uses small codebooks, and…”
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A novel methodology for power consumption reduction in a class of DSP algorithms by Masselos, K., Merakos, P., Stouraitis, T., Goutis, C.E.

“…In this paper a novel approach for low power realization of DSP algorithms that are based on inner product computation is proposed. Inner product computation…”
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Low-power image decoding using fractals by Masselos, K., Merakos, P., Stouraitis, T., Goutis, C.E.

“…In this paper a low-power evaluation of image decoding using fractals is presented. Fractal coding is asymmetrical in nature meaning that the encoder and the…”
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A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-[micro]m CMOS transceiver for 802.11a/b/g wireless LAN by Vavelidis, K, Vassiliou, I, Georgantas, T, Yamanaka, A, Kavadias, S, Kamoulakos, G, Kapnistis, C, Kokolakis, Y, Kyranas, A, Merakos, P, Bouras, I, Bouras, S, Plevridis, S, Haralabidis, N

“…A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-μm CMOS technology…”
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A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-mum CMOS transceiver for 802.11a/b/g wireless LAN by Vavelidis, K, Vassiliou, I, Georgantas, T, Yamanaka, A, Kavadias, S, Kamoulakos, G, Kapnistis, C, Kokolakis, Y, Kyranas, A, Merakos, P, Bouras, I, Bouras, S, Plevridis, S, Haralabidis, N

“…A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-mum CMOS technology. It…”
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A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN by Vavelidis, K., Vassiliou, I., Georgantas, T., Yamanaka, A., Kavadias, S., Kamoulakos, G., Kapnistis, C., Kokolakis, Y., Kyranas, A., Merakos, P., Bouras, I., Bouras, S., Plevridis, S., Haralabidis, N.

“…A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology…”
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A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18- mu m CMOS transceiver for 802.11a/b/g wireless LAN by Vavelidis, K, Vassiliou, I, Georgantas, T, Yamanaka, A, Kavadias, S, Kamoulakos, G, Kapnistis, C, Kokolakis, Y, Kyranas, A, Merakos, P, Bouras, I, Bouras, S, Plevridis, S, Haralabidis, N

“…A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18- mu m CMOS technology. It…”
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A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN by Vassiliou, I., Vavelidis, K., Georgantas, T., Plevridis, S., Haralabidis, N., Kamoulakos, G., Kapnistis, C., Kavadias, S., Kokolakis, Y., Merakos, P., Rudell, J.C., Yamanaka, A., Bouras, S., Bouras, I.

“…The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz…”
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A single-chip digitally calibrated 5.15-5.825-GHz 0.18-[micro]m CMOS transceiver for 802.11a wireless LAN by Vassiliou, I, Vavelidis, K, Georgantas, T, Plevridis, S, Haralabidis, N, Kamoulakos, G, Kapnistis, C, Kavadias, S, Kokolakis, Y, Merakos, P, Rudell, J.C, Yamanaka, A, Bouras, S, Bouras, I

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A single-chip digitally calibrated 5.15-5.825-GHz 0.18-mum CMOS transceiver for 802.11a wireless LAN by Vassiliou, I, Vavelidis, K, Georgantas, T, Plevridis, S, Haralabidis, N, Kamoulakos, G, Kapnistis, C, Kavadias, S, Kokolakis, Y, Merakos, P, Rudell, J C, Yamanaka, A, Bouras, S, Bouras, I

“…The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz…”
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A digitally calibrated 5.15-5.825GHz transceiver for 802.11a wireless LANs in 0.18/spl mu/m CMOS by Bouras, J., Bouras, S., Georgantas, T., Haralabidis, N., Kamoulakos, G., Kapnistis, C., Kavadias, S., Kokolakis, Y., Merakos, P., Rudell, J., Plevridis, S., Vassiliou, I., Vavelidis, K., Yamanaka, A.

“…This transceiver achieves a transmit 1dB output compression point of +15dBm, and the overall receiver noise figure is 5dB. A power gain range of >45dB/65dB for…”
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