Search Results - "Meleis, Waleed M."

Lower bounds on precedence-constrained scheduling for parallel processors by Baev, Ivan D., Meleis, Waleed M., Eichenberger, Alexandre

“…We consider two general precedence-constrained scheduling problems that have wide applicability in the areas of parallel processing, high performance…”
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Balance scheduling: weighting branch tradeoffs in superblocks by Eichenberger, A.E., Meleis, W.M.

“…Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling…”
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Efficient backtracking instruction schedulers by Abraham, S.G., Meleis, W.M., Baev, I.D.

“…Current schedulers for acyclic regions schedule operations in dependence order and never undo a scheduling decision. In contrast, backtracking schedulers may…”
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Backtracking-based instruction scheduling to fill branch delay slots by Baev, Ivan D, Meleis, Waleed M, Abraham, Santosh G

“…Conventional schedulers schedule operations in dependence order and never revisit or undo a scheduling decision on any operation. In contrast, backtracking…”
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Efficient Backtracking Instruction Schedulers by Abraham, Santosh G., Meleis, Waleed M., Baev, Ivan D.

“…Current schedulers for acyclic regions schedule operations in dependence order and never undo a scheduling decision. In contrast, backtracking schedulers may…”
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Rothko: a three-dimensional FPGA by Leeser, M., Meleis, W.M., Vai, M.M., Chiricescu, S., Weidong Xu, Zavracky, P.M.

“…Using transferred circuits and metal interconnections placed between layers of active devices anywhere on the chip, Rothko aims at solving utilization,…”
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Using data compression in automatic test equipment for system-on-chip testing by Karimi, F., Navabi, Z., Meleis, W.M., Lombardi, F.

“…Compression has been used in automatic test equipment (ATE) to reduce storage and application time for high volume data by exploiting the repetitive nature of…”
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Scheduling superblocks with bound-based branch trade-offs by Meleis, W.M., Eichenberger, A.E., Baev, I.D.

“…Since instruction level parallelism in basic blocks is often limited, compilers increase performance by creating superblocks that allow operations to be issued…”
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Optimal instruction scheduling and register allocation for multiple-issue processors by Meleis, Waleed M

“…As processors make use of wider instruction issue and deeper pipelines, the number of instructions in flight and consequently the number of simultaneously live…”
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Balance scheduling: weighting branch tradeoffs in superblocks by Eichenberger, Alexandre E., Meleis, Waleed M.

“…Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling…”
Get full text

Balance scheduling:weighting branch tradeoffs in superblocks by Eichenberger, Alexandre E, Meleis, Waleed M

“…Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling…”
Get full text