Search Results - "McMillan, K.L"
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Theory of latency-insensitive design
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-09-2001)“…The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling…”
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A methodology for hardware verification using compositional model checking
Published in Science of computer programming (01-05-2000)“…A methodology for system-level hardware verification based on compositional model checking is described. This methodology relies on a simple set of proof…”
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An interpolating theorem prover
Published in Theoretical computer science (21-11-2005)“…We present a method of deriving Craig interpolants from proofs in the quantifier-free theory of linear inequality and uninterpreted function symbols, and an…”
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Sibling-substitution-based BDD minimization using don't cares
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-01-2000)“…In many computer-aided design tools, binary decision diagrams (BDDs) are used to represent Boolean functions. To increase the efficiency and capability of…”
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Symbolic model checking for sequential circuit verification
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-04-1994)“…The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is modified to represent state graphs using binary decision diagrams (BDD's)…”
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Approximation and decomposition of binary decision diagrams
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998 (01-01-1998)“…Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the success of formal verification tools. Recent advances in…”
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Safe BDD Minimization Using Don't Cares
Published in Proceedings of the 34th Design Automation Conference (1997)Get full text
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A Structural Induction Theorem for Processes
Published in Information and computation (15-02-1995)“…This paper deals with the formal verification of finite state systems that hav an arbitrary number of isomorphic components. We present a technique for…”
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Spectral transforms for large boolean functions with applications to technology mapping
Published in 30th ACM/IEEE Design Automation Conference (01-07-1993)“…The Walsh transform has numerous applications in computer-aided design, but the usefulness of these techniques in practice has been limited by the size of the…”
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Analysis of digital circuits through symbolic reduction
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-11-1991)“…The authors describe a semi-algorithmic method to extract finite-state models from an analog circuit-level model by means of homomorphic (behavior preserving)…”
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A methodology for correct-by-construction latency insensitive design
Published in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) (1999)“…In deep sub-micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous…”
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Fitting formal methods into the design cycle
Published in 31st Design Automation Conference (06-06-1994)“…This tutorial introduces several methods of formal hardware verification that could potentially have a practical impact on the design process. The measure of…”
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A language for compositional specification and verification of finite state hardware controllers
Published in Proceedings of the IEEE (01-09-1991)“…The authors consider the state machine language (SML) for describing complex finite state hardware controllers. It provides many of the standard control…”
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Probabilistic state space search
Published in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) (1999)“…This paper describes a probabilistic approach to state space search. The presented method applies a ranking of the design states according to their probability…”
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Methods for exploiting SAT solvers in unbounded model checking
Published in First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings (2003)“…Modern SAT solvers have proved highly successful in finding counterexamples to temporal properties of systems, using a method known as "bounded model…”
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Feline trichomoniasis: an emerging disease?
Published in The Compendium on continuing education for the practicing veterinarian (01-06-2006)Get full text
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Sequential circuit verification using symbolic model checking
Published in 27th ACM/IEEE Design Automation Conference (1990)“…The temporal logic model algorithm of E.M. Clarke et al. (ACM Trans. Prog. Lang. Syst., vol.8, no.2, p.244-63, 1986) is modified to represent a state graph…”
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Engineering change in a non-deterministic FSM setting
Published in 33rd Design Automation Conference Proceedings, 1996 (1996)“…We propose a new formalism for the Engineering Change (EC) problem in a finite state machine (FSM) setting. Given an implementation that violates the…”
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Compositional model checking
Published in [1989] Proceedings. Fourth Annual Symposium on Logic in Computer Science (1989)“…A method is described for reducing the complexity of temporal logic model checking in systems composed of many parallel processes. The goal is to check…”
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