SiGe FinFET for practical logic libraries by mitigating local layout effect

SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is chann...

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Bibliographic Details
Published in:	2017 Symposium on VLSI Technology pp. T122 - T123
Main Authors:	Tsutsui, Gen, Huimei Zhou, Greene, Andrew, Robison, Robert, Jie Yang, Juntao Li, Prindle, Christopher, Sporre, John R., Miller, Eric R., Liu, Derrick, Sporer, Ryan, Mulfinger, Bob, McArdle, Tim, Jin Cho, Karve, Gauri, Fee Li Lie, Kanakasabapathy, Siva, Carter, Rick, Gupta, Dinesh, Knorr, Andreas, Dechao Guo, Huiming Bu
Format:	Conference Proceeding
Language:	English
Published:	JSAP 01-06-2017
Subjects:	Epitaxial growth FinFETs Lattices Layout Logic gates Silicon germanium Strain
Online Access:	Get full text
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Summary:	SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined LLE in SiGe pFinFET and explored its mitigation techniques. Two techniques are proposed and demonstrated successful LLE mitigation, which drives forward SiGe FinFET insertion to technology.
ISSN:	2158-9682
DOI:	10.23919/VLSIT.2017.7998215