Search Results - "Matsuoka, Fumitomo"

Accurate Measurement of Silicide Specific Contact Resistivity by Cross Bridge Kelvin Resistor for 28 nm Complementary Metal--Oxide--Semiconductor Technology and Beyond by Ohuchi, Kazuya, Kusunoki, Naoki, Matsuoka, Fumitomo

“…In scaling down the device feature size, a reduction in parasitic resistance is inevitable in realizing a high-performance complimentary…”
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Accurate Measurement of Silicide Specific Contact Resistivity by Cross Bridge Kelvin Resistor for 28 nm Complementary Metal–Oxide–Semiconductor Technology and Beyond by Ohuchi, Kazuya, Kusunoki, Naoki, Matsuoka, Fumitomo

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Optimization of Stress Memorization Technique for 45 nm Complementary Metal–Oxide–Semiconductor Technology by Morifuji, Eiji, Eiho, Ayumi, Sanuki, Tomoya, Iwai, Masaaki, Matsuoka, Fumitomo

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The Impact of Technology Scaling for RF Complementary Metal–Oxide–Semiconductor by Morifuji, Eiji, Kimijima, Hideki, Kojima, Kenji, Iwai, Masaaki, Matsuoka, Fumitomo

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Study of Unique ESD Tolerance Dependence on Backgate Ratio for RESURF LDMOS with Rated Voltage Variation by Komatsu, Kanako, Ozaki, Koichi, Takeuchi, Fumio, Shinohara, Daisuke, Kinoshita, Tomoko, Ishii, Yoshiaki, Sakamoto, Toshihiro, Matsuoka, Fumitomo

“…This paper describes that an unique ESD tolerance dependence on a backgate ratio of fully isolated RESURF LDMOS for various cases of rated voltage. For the…”
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Investigation of the Breakdown Voltage Degradation under Hot-Carrier Injection in STI-based PchLDMOS Transistors by Kasai, Hirotaka, Shinohara, Daisuke, Shimizu, Mariko, Ishii, Yoshiaki, Komatsu, Kanako, Sakamoto, Toshihiro, Yonemura, Koji, Matsuoka, Fumitomo

“…Hot-carrier injection causes characteristics change of semiconductor devices. In this work, off-state breakdown voltage (BVdss) degradation of shallow trench…”
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Investigating the Highly Tolerant LDMOS Cell Array Design against the Negative Carrier Injection and the ESD Events by Komatsu, Kanako, Shinohara, Daisuke, Shimizu, Mariko, Ishii, Yoshiaki, Sakamoto, Toshihiro, Yonemura, Koji, Matsuoka, Fumitomo

“…Optimum LDMOS array layout design is proposed which is tolerant against not only the negative carrier injection but also the ESD events. Both are indispensable…”
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Hot-carrier induced off-state leakage current increase of LDMOS and approach to overcome the phenomenon by Takahashi, Keita, Komatsu, Kanako, Sakamoto, Toshihiro, Kimura, Koji, Matsuoka, Fumitomo, Ishii, Yoshiaki, Egashira, Katsumi, Sakai, Masaki

“…We found and reported the unique drastic Ioff increase of LDMOS caused by HC induced trapped charge in the STI under the off-state condition. In this paper, we…”
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HBM robustness optimization of fully isolated Nch-LDMOS for negative input voltage using unique index parameter by Takeuchi, Fumio, Nagano, Hirofumi, Sakamoto, Toshihiro, Kimura, Koji, Matsuoka, Fumitomo

“…To overcome the trade-off between breakdown voltage to negative bias and HBM robustness in fully isolated Nch-LDMOS, we found and utilized a new unique…”
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Counter-Doped Surface Channel Metal-Oxide-Semiconductor Field-Effect Transistor with High Current Drivability and Steep Subthreshold Slope by Koike, Hidetoshi, Enda, Toshiyuki, Matsuoka, Fumitomo, Shigyo, Naoyuki

“…A metal-oxide-semiconductor field-effect transistor (MOSFET) with a novel channel structure called a counter-doped surface channel (CDSC) is proposed. A unique…”
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Design Method and Mechanism Study of LDMOS to Conquer Stress Induced Degradation of Leakage Current and HTRB Reliability by Komatsu, Kanako, Kinoshita, Tomoko, Shioda, Saori, Sakamoto, Toshihiro, Kimura, Koji, Yonemura, Koji, Matsuoka, Fumitomo, Takahashi, Keita, Urata, Akihiro, Sakaguchi, Shoichi, Nagamatsu, Takahito

“…8V NchLDMOS, which has an enough tolerance against both a leakage current (Idss) increase and high temperature reverse bias (HTRB) degradation is proposed…”
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Novel procedure to improve LDMOS ESD characteristics by optimizing drain structure by Komatsu, Kanako, Takahashi, Keita, Sakurai, Tadaomi, Ikimura, Takehito, Sakai, Masaki, Kimura, Koji, Matsuoka, Fumitomo

“…Novel procedure to realize a high ESD robustness with small variation for 40V p-ch LDMOS is proposed. By optimizing the drain structure, current flow path…”
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Supply and threshold-Voltage trends for scaled logic and SRAM MOSFETs by Morifuji, E., Yoshida, T., Kanda, M., Matsuda, S., Yamada, S., Matsuoka, F.

“…The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low…”
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Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique by Morifuji, E., Aikawa, H., Yoshimura, H., Sakata, A., Ohta, M., Iwai, M., Matsuoka, F.

“…Layout dependences for stress-enhanced MOSFETs including contact positioning, the second neighboring poly effect, and bent diffusion are modeled in 45-nm CMOS…”
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Low-resistivity poly-metal gate electrode durable for high-temperature processing by Akasaka, Y., Suehiro, S., Nakajima, K., Nakasugi, T., Miyano, K., Kasai, K., Oyamatsu, H., Kinugawa, M., Takagi, M.T., Agawa, K., Matsuoka, F., Kakumu, M., Suguro, K.

“…A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100…”
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Increase of parasitic resistance in shallow p super(+) extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25- mu m pMOSFET's by Inaba, Satoshi, Murakoshi, Atsushi, Tanaka, Miwa, Yoshimura, Hisao, Matsuoka, Fumitomo, Toyoshima, Yoshiaki

“…Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25- mu m pMOSFET's. The parasitic resistance in p…”
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Dual-polycide gate technology using regrowth amorphous-Si to suppress lateral dopant diffusion by Koike, H., Unno, Y., Matsuoka, F., Kakumu, M.

“…Process techniques for dual-polycide gate CMOS have been developed. The origin of lateral dopant diffusion is analyzed, and an enlarged-grain dual-polycide…”
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Analysis of hot-carrier-induced degradation mode on pMOSFET's by Matsuoka, F., Iwai, H., Hayashida, H., Hama, K., Toyoshima, Y., Maeguchi, K.

“…Hot-carrier-induced degradation surface-channel (p/sup +/ polysilicon gate) and buried-channel (n/sup +/ polysilicon gate) pMOSFETs is discussed. In the…”
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Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET by Matsuoka, F., Kasai, K., Oyamatsu, H., Kinugawa, M., Maeguchi, K.

“…A guideline for n/sup /spl minus// fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, the greatest…”
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Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's by Toyoshima, Y., Iwai, H., Matsuoka, F., Hayashida, H., Maeguchi, K., Kanzaki, K.

“…The analysis indicates that a thinner gate oxide nMOSFET shows smaller degradation. Mechanisms for the smaller degradation were analyzed using a simple…”
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