Search Results - "Masuda, Takatoshi"

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  1. 1

    Warpage Reduction and Thermal Stress Study of Dicing Process in Wafer-to-Wafer Bonding Fabrication by Feng, Wei, Shimamoto, Haruo, Kawagoe, Tsuyoshi, Honma, Ichirou, Yamasaki, Masato, Okutsu, Fumitake, Masuda, Takatoshi, Kikuchi, Katsuya

    Published in IEEE transactions on electron devices (01-11-2022)
    “…We successfully study the warpage after wafer-to-wafer (W2W) bonding by the experiments and the full wafer model simulation. Furthermore, the effect of the…”
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    Journal Article
  2. 2

    Wafer-to-Wafer Bonding Fabrication Process-Induced Wafer Warpage by Feng, Wei, Shimamoto, Haruo, Kawagoe, Tsuyoshi, Honma, Ichirou, Yamasaki, Masato, Okutsu, Fumitake, Masuda, Takatoshi, Kikuchi, Katsuya

    “…Wafer warpage affects the resolution of photolithography, process alignment, and wafer bonding, which leads to the degradation of the device's yield,…”
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    Journal Article
  3. 3

    Study of wafer warpage reduction by dicing street by Feng, Wei, Shimamoto, Haruo, Kawagoe, Tsuyoshi, Honma, Ichirou, Yamasaki, Masato, Okutsu, Fumitake, Masuda, Takatoshi, Kikuchi, Katsuya

    Published in Japanese Journal of Applied Physics (01-08-2022)
    “…Wafer warpage occurs during the fabrication process, which induces many issues such as wafer handling, lithography alignment, device reliability. The…”
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    Journal Article
  4. 4

    Multi Die Stacked Structure Fabricated by WoW Bonding by Shimamoto, Haruo, Araga, Yuuki, Fujino, Masahisa, Watanabe, Naoya, Takahashi, Kenji, Kikuchi, Katsuya, Kawagoe, Tsuyoshi, Homma, Ichiro, Masuda, Takatoshi

    Published in 2023 IEEE CPMT Symposium Japan (ICSJ) (15-11-2023)
    “…To achieve 2-die stacking process, fusion bonding technology was applied for Wafer on Wafer (WoW) by each oxide film, and Through Silicon Via (TSV) was used to…”
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    Conference Proceeding