Search Results - "Marchand, Cedric"
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Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators
Published in IEEE transactions on information forensics and security (01-06-2016)“…This paper proposes a theoretical study and a full overview of the design, evaluation, and optimization of a PUF based on transient element ring oscillators…”
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2
3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs
Published in IEEE journal on exploratory solid-state computational devices and circuits (01-12-2023)“…This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal…”
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3
3D Logic circuit design oriented electrothermal modeling of vertical junctionless nanowire FETs
Published in IEEE journal on exploratory solid-state computational devices and circuits (01-12-2023)“…This work presents new insights into 3D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal…”
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4
A FeFET-Based Hybrid Memory Accessible by Content and by Address
Published in IEEE journal on exploratory solid-state computational devices and circuits (01-06-2022)“…Emerging nonvolatile memory technologies are attracting interest from the system design level to implement alternatives to conventional von-Neumann computing…”
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Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-01-2018)“…Today, life is becoming increasingly connected. From TVs to smartphones, including vehicles, buildings, and household appliances, everything is interconnected…”
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6
Reconfigurable Multifunctional van der Waals Ferroelectric Devices and Logic Circuits
Published in ACS nano (14-11-2023)“…Emerging reconfigurable devices are fast gaining popularity in the search for next-generation computing hardware, while ferroelectric engineering of the doping…”
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7
Buffers optimization for multi-core decoders
Published in 2023 IEEE Wireless Communications and Networking Conference (WCNC) (01-03-2023)“…For very high-speed satellite communication (up to 10 Gbit/s), the natural level of parallelism of a single decoder might be insufficient to achieve the…”
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Conference Proceeding -
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The Best, the Requested, and the Default Elementary Check Node for EMS NB-LDPC Decoder
Published in 2023 IEEE Wireless Communications and Networking Conference (WCNC) (01-03-2023)“…Non-Binary LDPC codes are known to have good decoding capability and high decoding complexity. Therefore, their utilization is limited to low-rate applications…”
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Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing
Published in Journal of signal processing systems (01-10-2022)“…This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new…”
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10
Hybrid Check Node Architectures for NB-LDPC Decoders
Published in IEEE transactions on circuits and systems. I, Regular papers (01-02-2019)“…This paper proposes a unified framework to describe the check node architectures of non-binary low-density parity-check (NB-LDPC) decoders. Forward-backward,…”
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11
Area‐oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti‐counterfeiting schemes
Published in International journal of circuit theory and applications (01-02-2017)“…Summary Over the past 10 years, the multitude of highly constrained applications such as radio‐frequency identification and sensor networks has led to a new…”
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12
Identification of IP control units by state encoding and side channel verification
Published in Microprocessors and microsystems (01-11-2016)“…Synchronous finite state machines (FSMs) are the backbone of an embedded controller design. We propose a non-destructive watermark embedding algorithm and a…”
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13
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model
Published in 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC) (05-10-2020)“…Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices., which are well suited to pursue scaling beyond lateral scaling…”
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Conference Proceeding -
14
Simplified Compression of Redundancy Free Trellis Sections in Turbo Decoder
Published in IEEE communications letters (01-06-2014)“…It has been recently shown that a sequence of R = q(M - 1) redundancy free trellis stages of a recursive convolutional decoder can be compressed in a sequence…”
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FVLLMONTI: The 3D Neural Network Compute Cube (N^C^) Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation
Published in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) (25-03-2024)“…This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and…”
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Architecture and Finite Precision Optimization for Layered LDPC Decoders
Published in Journal of signal processing systems (01-11-2011)“…Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, two main issues affect performance and area of…”
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IP watermark verification based on power consumption analysis
Published in 2014 27th IEEE International System-on-Chip Conference (SOCC) (01-09-2014)“…The increasing production costs of electronic devices and changes in the design methods of integrated circuits (ICs) has led to emerging threats in the…”
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18
Conflict resolution for pipelined layered LDPC decoders
Published in 2009 IEEE Workshop on Signal Processing Systems (01-10-2009)“…Many of the current LDPC implementations of DVB-S2, T2 or WiMAX standard use the so-called layered architecture combined with pipeline. However, the pipeline…”
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VNWFET-Based Technology: From Device Modelling to Standard Cell Library
Published in 2023 IEEE 23rd International Conference on Nanotechnology (NANO) (02-07-2023)“…Vertical Nanowire Field Effect Transistors (VN-WFETs) are an emerging technology with significant potential to reduce footprint and consequently interconnect…”
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Security Layers and Related Services within the Horizon Europe NEUROPULS Project
Published in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) (25-03-2024)“…In the contemporary security landscape, the incorporation of photonics has emerged as a transformative force, unlocking a spectrum of possibilities to enhance…”
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Conference Proceeding