Search Results - "Manley, M. H."

A high-speed ultra-low power 64 K CMOS EPROM with on-chip test functions by KNECHT, M. W, MANLEY, M. H, PERASSO, D. C, THOMAS, J. F, KESHTBOD, P, NARESH TANDAN, SIMMONS, G. H

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A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions by Knecht, M.W., Manley, M.H., Perasso, D.C., Thomas, J.F., Keshtbod, P., Tandan, N., Simmons, G.H.

“…A 100 ns 8K /spl times/ 8 CMOS EPROM has been developed. Internal clock signals generated by address transition detection are used to reduce power consumption…”
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Computer-Aided Custom LSI Design with the ULA by Prazic, B. D., Stenton, J. A. C., Manley, M. H., Mole, P. J.

“…A complete suite of computer programs is described for custom LSI design with the ULA. The Array is designed in silicon-gate CMOS/SOS and contains 512 cells…”
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A modular 1 mu m CMOS single polysilicon EPROM PLD technology by Cacharelis, P.J., Hart, M.J., Manley, M.H., Frake, S.O., Knecht, M.W.

“…The authors describe a single-polysilicon CMOS process that has been optimized for the production of high-speed programmable logic devices (PLDs). The process…”
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A systematic test methodology for identifying defect-related failure mechanisms in an EEPROM technology by Hoffstetter, D.M., Manley, M.H.

“…A new test methodology is described for identifying defect-related failures of EEPROM memory cells. Currently, tunnel oxide Qbd tests are widely used to…”
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A fully modular 1 μm CMOS technology incorporating EEPROM, EPROM and interpoly capacitors by Cacharelis, Philip J, Hart, Michael J, Wolstenholme, Graham R, Carpenter, Roger D, Johnson, Ian F, Manley, Martin H

“…This paper will describe a modular technology which uses a novel integration scheme to include double poly EEPROM, single poly EPROM and an interpoly…”
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