Search Results - "Malhi, S.D.S."

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon by Malhi, S.D.S., Shichijo, H., Banerjee, S.K., Sundaresan, R., Elahy, M., Pollack, G.P., Richardson, W.F., Shah, A.H., Hite, L.R., Womack, R.H., Chatterjee, P.K., Lam, H.W.

“…Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that…”
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Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon by Malhi, S.D.S., Shichijo, H., Banerjee, S.K., Sundaresan, R., Elahy, M., Pollack, G.P., Richardson, W.F., Shah, A.H., Hite, L.R., Womack, R.H., Chatterjiee, P.K., Hon Wai Lam

“…Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that…”
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Process and performance comparison of an 8K × 8-bit SRAM in three stacked CMOS technologies by Hite, L.R., Sundaresan, R., Malhi, S.D.S., Lam, H.W., Shah, A.H., Hester, R.K., Chatterjee, P.K.

“…Using self-aligned and non-self-aligned stacked CMOS technologies experimental 8K × 8-bit static random-access memories (SRAM'S) have been fabricated. Hydrogen…”
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Hydrogen passivation of PolySilicon MOSFET's from a plasma Nitride source by Pollack, G.P., Richardson, W.F., Malhi, S.D.S., Bonifield, T., Shichijo, H., Banerjee, S., Elahy, M., Shah, A.H., Womack, R., Chatterjee, P.K.

“…Improvements in polysilicon grain-boundary passivation techniques have made polysilicon MOSFET's increasingly attractive, as vertically stackable circuit…”
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A 4-Mbit DRAM with trench-transistor cell by Shah, A.H., Wang, C., Womack, R.H., Gallia, J.D., Shichijo, H., Davis, H.E., Elahy, M., Banerjee, S.K., Pollack, G.P., Richardson, W.F., Bordelon, D.M., Malhi, S.D.S., Pilch, C.J., Tran, B., Chatterjee, P.K.

“…An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology…”
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Stacked CMOS SRAM cell by Chen, C.-E., Lam, H.W., Malhi, S.D.S., Pinizzotto, R.F.

“…A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are…”
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VB-3 stacked CMOS sRAM cell by Chen, C.-E., Lam, H.W., Malhi, S.D.S., Pinizzotto, R.F.

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Thermal annealing behavior of an oxide layer under silicon by Hamdi, A. H., McDaniel, F. D., Pinizzotto, R. F., Matteson, S., Lam, H. W., Malhi, S. D. S.

“…High resolution Rutherford backscattering spectrometry and ion channeling have been employed to evaluate the crystallinity of the surface silicon layer in…”
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Novel SOI CMOS design using ultra thin near intrinsic substrate by Malhi, S.D.S., Lam, H.W., Pinizzotto, R.F., Hamdi, A.H., McDaniel, F.D.

“…A novel SOI CMOS design has been explored. It utilizes an ultra thin near intrinsic substrate wherein no channel doping is introduced during processing. The…”
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A low-voltage micropower JFET/bipolar operational amplifier by Malhi, S.D.S., Salama, C.A.T., Donnison, W.R.

“…A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction…”
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VB-5 comparison of accumulation and inversion mode LPCVD polysilicon MOSFET characteristics for memory applications by Banerjee, S.K., Elahy, M., Shichijo, H., Pollack, G.P., Richardson, W.F., Malhi, S.D.S., Shah, A.H., Chatterjee, P.K., Lam, H.W., Womack, R.H.

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VB-1 a VLSI suitable 2-µm stacked CMOS process by Malhi, S.D.S., Karnaugh, R., Shah, A.H., Hite, L., Chatterjee, P.K., Davis, H.E., Mahant-Shetti, S.S., Gosmeyer, C.D., Sundaresan, R.S., Chen, C.E., Lam, H.W., Haken, R.A., Pinizzotto, R.F., Hester, R.K.

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VB-1 characteristics of p-channel MOSFETs in LPCVD polysilicon and effect of grain boundary passivation on device performance by Malhi, S.D.S., Shah, R.R., Chatterjee, P.K., Lam, H.W., Pinizzoto, R.F., Chen, C.E.C., Shichijo, H., Bellavance, D.W.

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p-Channel MOSFET's in LPCVD PolySilicon by Malhi, S.D.S., Chatterjee, P.K., Pinizzotto, R.F., Lam, H.W., Chen, C.E.C., Shichijo, H., Shah, R.R., Bellavance, D.W.

“…p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-Å n + poly acts as the gate electrode on which a 500-Å thermal oxide is grown to act as…”
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Subsurface junction field effect transistor by Malhi, S.D.S., Salama, C.A.T., Donnison, W.R., Barber, H.D.

“…A novel bipolar compatible junction field effect transistor structure is described in this paper. The device is fabricated using a single boron implant at…”
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Edge-defined self-alignment of submicrometer overlaid devices by Malhi, S.D.S., Chatterjee, P.K., Bonifield, T.D., Leiss, J.E., Carter, D.E., Pinizzotto, R.F., Coleman, D.J.

“…A novel device structure for self-aligning the overlaid device in a stacked CMOS process is introduced and demonstrated. The structure allows submicrometer…”
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Trench transistor DRAM cell by Shichijo, H., Banerjee, S.K., Malhi, S.D.S., Pollack, G.P., Richardson, W.F., Bordelon, D.M., Womack, R.H., Elahy, M., Wang, C.-P., Gallia, J., Davis, H.E., Shah, A.H., Chatterjee, P.K.

“…A new one-transistor DRAM cell with both the transistor and the capacitor fabricated on the trench sidewalls is described. With the signal stored on the…”
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A fully self-aligned stacked CMOS 64K SRAM by Sundaresan, R., Malhi, S.D.S., Hite, L.R., Shah, A.H., Lam, H.W., Chatterjee, P.K.

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SOI CMOS circuit performance on graphite strip heater recrystallized material by Malhi, S.D.S., Lam, H.W., Pinizzotto, R.F.

“…A CMOS process has been implemented on graphite strip heater recrystallized silicon substrates. The low field electron mobility of 660 cm 2 /V.sec and hole…”
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Orthogonal chip mount - A 3D hybrid wafer scale integration technology by Malhi, S.D.S., Davis, H.E., Stierman, R.J., Bean, K.E., Driscoll, C.C., Chatterjee, P.K.

“…In the last decade, device scaling in the integrated circuit technology has permitted a drastic improvement in the density of electronic systems. This trend…”
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