Search Results - "Makosiej, Adam"

A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology by El Husseini, Joanna, Garros, Xavier, Cluzel, Jacques, Subirats, Alexandre, Makosiej, Adam, Weber, Olivier, Thomas, Olivier, Huard, Vincent, Federspiel, Xavier, Reimbold, Gilles

“…In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability…”
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A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm by Christmann, Jean-Frédéric, Berthier, Florent, Coriat, David, Miro-Panades, Ivan, Guthmuller, Eric, Thuries, Sébastien, Thonnart, Yvain, Makosiej, Adam, Debicki, Olivier, Heitzmann, Frédéric, Valentian, Alexandre, Vivet, Pascal, Beigné, Edith

“…Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off…”
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Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C CAM by Gupta, Navneet, Makosiej, Adam, Shrimali, Hitesh, Amara, Amara, Vladimirescu, Andrei, Anghel, Costin

“…A refresh free and scalable ultimate DRAM (uDRAM) with 1T1C bitcell is introduced in this paper. The memory uses the Negative Differential Resistance (NDR)…”
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SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration by Miro-Panades, Ivan, Tain, Benoit, Christmann, Jean-Frederic, Coriat, David, Lemaire, Romain, Jany, Clement, Martineau, Baudouin, Chaix, Fabrice, Waltener, Guillaume, Pluchart, Emmanuel, Noel, Jean-Philippe, Makosiej, Adam, Montoya, Maxime, Bacles-Min, Simone, Briand, David, Philippe, Jean-Marc, Thonnart, Yvain, Valentian, Alexandre, Heitzmann, Frederic, Clermidy, Fabien

“…Increased capabilities, such as recognition and self-adaptability, are now required from Internet-of-Things (IoT) applications. While IoT node power…”
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CMOS Sensor Nodes With Sub-Picowatt TFET Memory by Gupta, Navneet, Makosiej, Adam, Anghel, Costin, Amara, Amara, Vladimirescu, Andrei

“…This paper describes the applicability of tunnel FETs (TFET) to ultra-low-power sensor-node embedded static random-access memories (SRAMs). Numerical TCAD…”
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Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC by Gupta, Navneet, Shrimali, Hitesh, Makosiej, Adam, Vladimirescu, Andrei, Amara, Amara

“…This paper presents a novel TFET-CMOS co-integrated comparator-less, energy-efficient ADC architecture. The design utilizes the Negative Differential…”
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3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications by Gupta, Navneet, Makosiej, Adam, Vladimirescu, Andrei, Amara, Amara, Anghel, Costin

“…This paper presents a TFET/CMOS hybrid SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like IoT (Internet of…”
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Tunnel FET based refresh-free-DRAM by Gupta, Navneet, Makosiej, Adam, Vladimirescu, Andrei, Amara, Amara, Anghel, Costin

“…A refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access…”
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16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell by Gupta, Navneet, Makosiej, Adam, Vladimirescu, Andrei, Amara, Amara, Anghel, Costin

“…This paper presents for the first time a TFET/CMOS hybrid CAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications like the…”
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Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up by Hraziia, Makosiej, Adam, Palma, Giorgio, Portal, Jean-Michel, Bocquet, Marc, Thomas, Olivier, Clermidy, Fabien, Reyboz, Marina, Onkaraiah, Santhosh, Muller, Christophe, Deleruyelle, Damien, Vladimirescu, Andrei, Amara, Amara, Anghel, Costin

“…► We designed an NVSRAM cell with 22 nm FDSOI PDK for CMOS and HfO2 OxRRAMs. ► We showed that our NVSRAM cell is operational at high speed (20ns) and low…”
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Mixed-single well 8T SRAM bitcell for wide voltage range in 28nm FDSOI by Makosiej, Adam, Planes, N., Ranica, R., Ciampolini, L., Thomas, Olivier

“…Enabling high speed SRAM operation at low voltage is typically limited by variability and low device drivability. Most of the reported low-voltage SRAM…”
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1.45-fJ/bit Access Two-Port SRAM Interfacing a Synchronous/Asynchronous IoT Platform for Energy-Efficient Normally Off Applications by Boumchedda, Reda, Makosiej, Adam, Noel, Jean-Philippe, Giraud, Bastien, Christmann, Jean-Frederic, Miro-Panades, Ivan, Ciampolini, Lorenzo, Royer, Pablo, Mounet, Christopher, Turgis, David, Beigne, Edith

“…This letter presents a single-rail two-port static random-access memory (SRAM) designed in 28-nm FD-SOI technology specifically for a synchronous/asynchronous…”
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CMOS SRAM scaling limits under optimum stability constraints by Makosiej, Adam, Thomas, Olivier, Amara, Amara, Vladimirescu, Andrei

“…This paper presents a predictive analysis of the high-density SRAM cell scaling from the stability and low power perspective. Based on a subthreshold SRAM…”
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SRAM row decoder design for wide voltage range in 28nm UTBB-FDSOI by Suraci, Gregory, Giraud, Bastien, Benoist, Thomas, Makosiej, Adam, Thomas, Olivier

“…This paper focuses on the design of SRAM row decoder for modern portable devices, in 28nm Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted SOI (FDSOI)…”
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Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization by Makosiej, Adam, Thomas, Olivier, Vladimirescu, Andrei, Amara, Amara

“…This paper presents a methodology for the optimal design of CMOS 6T SRAM ultra-low-power (ULP) bitcells minimizing power consumption under strict stability…”
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Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications by Gupta, N., Makosiej, A., Thomas, O., Amara, A., Vladimirescu, A., Anghel, C.

“…In this paper, an ultra-low-leakage TFET/CMOS hybrid Dual-Port SRAM (DPSRAM) based scratchpad memory is proposed. DPSRAM cells are designed using TFETs to…”
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Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization by Makosiej, A., Thomas, O., Vladimirescu, A., Amara, A.

“…This paper presents a methodology for the optimal design of CMOS 6T SRAM ultra-low-power (ULP) bitcells minimizing power consumption under strict stability…”
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A 32nm tunnel FET SRAM for ultra low leakage by Makosiej, A., Kashyap, R. K., Vladimirescu, A., Amara, A., Anghel, C.

“…This paper describes the applicability of Tunnel FETs to commercial embedded Static Random-Access Memories (SRAM). Numerical device simulations were used first…”
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SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency by Miro-Panades, Ivan, Tain, Benoit, Christmann, Jean-Frederic, Coriat, David, Lemaire, Romain, Jany, Clement, Martineau, Baudouin, Chaix, Fabrice, Quelen, Anthony, Pluchart, Emmanuel, Noel, Jean-Philippe, Boumchedda, Reda, Makosiej, Adam, Montoya, Maxime, Bacles-Min, Simone, Briand, David, Philippe, Jean-Marc, Valentian, Alexandre, Heitzmann, Frederic, Beigne, Edith, Clermidy, Fabien

“…IoT node application requirements are torn between sporadic data-logging and energy-hungry data processing (e.g. image classification). This paper presents a…”
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Double-Gate Sub-32nm CMOS SRAM current and voltage sense amplifiers, insensitive to process variations and transistor mismatch by Makosiej, Adam, Nasalski, Piotr, Giraud, Bastien, Vladimirescu, Andrei, Amara, Amara

“…This paper describes two novel sub-32 nm current (CSA) and voltage (VSA) sense amplifiers in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI)…”
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