Search Results - "Mahlstedt, U."

CURRENT: a test generation system for I/sub DDQ/ testing by Mahlstedt, U., Alt, J., Heinitz, M.

“…This paper presents an I/sub DDQ/ test generation system for scan-based circuits, called CURRENT. A library-based fault modeling strategy is used to specify a…”
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DELTEST: Deterministic test generation for gate delay faults by Mahlstedt, U.

“…This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a "good" delay test the…”
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Simulation of non-classical faults on the gate level-fault modeling by Alt, J., Mahlstedt, U.

“…A two-step approach is used to increase the accuracy of fault modeling without sacrificing the efficiency of fault simulation and test pattern generation on…”
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Deterministic test generation for non-classical faults on the gate level by Mahlstedt, U., Alt, J., Hollenbeck, I.

“…This paper presents a deterministic test pattern generator for combinational circuits, called CONTEST, which can efficiently handle various gate level fault…”
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Test generation for I/sub DDQ/ testing and leakage fault detection in CMOS circuits by Mahlstedt, U., Heinitz, M., Alt, J.

“…The authors describe a two-stage method to generate test sets for quiescent power supply current, I/sub DDQ/, testing and to determine the leakage fault…”
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DIATEST: a fast diagnostic test pattern generator for combinational circuits by Gruning, T., Mahlstedt, U., Koopmeiners, H.

“…The authors present an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The…”
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Simulation of non-classical faults on the gate level - The fault simulator COMSIM by Mahlstedt, U., Alt, J.

“…COMSIM is a fault simulator for combinational circuits which can efficiently handle various gate level fault models. Stuck-at faults, function conversions,…”
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Accelerated test pattern generation by cone-oriented circuit partitioning by Gruning, T., Mahlstedt, U., Daehn, W., Ozcan, C.

“…An efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational…”
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Accelerated test pattern generation by cone-oriented circuit partitioning by Grüning, T., Mahlstedt, U., Daehn, W., Özcan, C.

“…In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for…”
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Contest: a fast ATPG tool for very large combinational circuits by Mahlstedt, U., Gruning, T., Ozcan, C., Daehn, W.

“…Contest (cone-oriented test pattern generator), an ATPG (automatic test pattern generation) tool for very large combinational digital circuits, is presented…”
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