Search Results - "Magarshack, P."
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Guest Editors' Introduction: Design for Yield and Reliability
Published in IEEE design & test of computers (01-05-2004)“…Presents the guest editorial for this issue of the publication…”
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Improving SoC design quality through a reproducible design flow
Published in IEEE design & test of computers (01-01-2002)“…The author examines the dynamics of system-on-a-chip design and addresses the fundamental question of whether there is a reproducible process for achieving the…”
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Low-Power Design Solutions for Wireless Multimedia SoCs
Published in IEEE design & test of computers (01-03-2009)“…With advanced semiconductor technology nodes, power management has become a global problem. In battery powered applications, this problem is even more…”
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System-on-chip beyond the nanometer wall
Published in Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) (02-06-2003)“…In this paper, we analyze the emerging trends in the design of complex Systems-on-a-Chip for nanometer-scale semiconductor technologies and their impact on…”
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Conference Proceeding
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"The IC nanometer race -- what will it take to win?"
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 43rd annual conference on Design automation; 24-28 July 2006 (24-07-2006)“…Creating ICs in the nanometer age is a high-stakes race that few companies can afford to compete in - and even fewer can win. Hear how senior technologists…”
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Building yield into systems-on chips for nanometer technologies
Published in Proceedings. 21st VLSI Test Symposium, 2003 (2003)Get full text
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Design challenges and emerging EDA solutions in mixed-signal IC design
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe (13-03-2001)Get full text
Conference Proceeding -
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Beyond the horizon: The next 10x reduction in power - Challenges and solutions
Published in 2011 IEEE International Solid-State Circuits Conference (01-02-2011)“…Summary form only given. The energy efficiency of electronic circuits has dramatically improved over the past two decades. At the same time, computation,…”
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Datapath implementation: bit-slice structure versus standard cells
Published in Euro ASIC '92 (1992)“…In some CAD systems, the implementation of regular or semi-regular datapaths is eased by providing specific tools, called 'datapath compilers'. These tools…”
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Panel: "DFM/DFY: Should You Trust the Surgeon or the Family Doctor?"
Published in 2007 Design, Automation & Test in Europe Conference & Exhibition (01-04-2007)“…Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to…”
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Gaining 10x in energy efficiency in the next decade in consumer products
Published in Proceedings of Technical Program of 2012 VLSI Design, Automation and Test (01-04-2012)“…In the last two decades, Semiconductors have successively enabled disruptive market expansions in the PC, consumer and Mobility markets. Electronics have now…”
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Conference Proceeding -
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DAC technologist panel "the IC nanometer race - what will it take to win"
Published in 2006 43rd ACM/IEEE Design Automation Conference (2006)“…Creating ICs in the nanometer age is a high-stakes race that few companies can afford to compete in - and even fewer can win. Hear how senior technologists…”
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Conference Proceeding -
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A fast data path multiplier
Published in Euro ASIC '91 (1991)“…The authors describe a highly configurable, compiled, fast data path multiplier implemented in the CSAM ASIC technology-independent library based on the…”
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Computer aids for high performance CMOS custom design
Published in 1989 Proceedings of the IEEE Custom Integrated Circuits Conference (1989)“…A set of design tools that creates the framework for a loading-edge full-custom design methodology has been developed. The tools provide the design flexibility…”
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Fast, cheap and under control: the next implementation fabric
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation (02-06-2003)Get full text
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Comprehensive CAD support for boundary scan implementation in ASICs
Published in Euro ASIC '91 (1991)“…The authors review the complete automated implementation of the IEEE P1149.1 boundary scan standard proposed in the CSAM ASIC compiled technology-independent…”
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Conference Proceeding
