Search Results - "MONTOYE, Robert K"

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches by Chang, L., Montoye, R.K., Nakamura, Y., Batson, K.A., Eickemeyer, R.J., Dennard, R.H., Haensch, W., Jamsek, D.

“…An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be…”
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Practical Strategies for Power-Efficient Computing Technologies by Chang, Leland, Frank, David J., Montoye, Robert K., Koester, Steven J., Ji, Brian L., Coteus, Paul W., Dennard, Robert H., Haensch, Wilfried

“…After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by…”
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1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing by Jing Li, Montoye, Robert K., Ishii, Masatoshi, Chang, Leland

“…This work demonstrates the first fabricated 1 Mb nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than…”
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Energy Efficiency Boost in the AI-Infused POWER10 Processor by Thompto, Brian W., Nguyen, Dung Q., Moreira, Jose E., Bertran, Ramon, Jacobson, Hans, Eickemeyer, Richard J., Rao, Rahul M., Goulet, Michael, Byers, Marcy, Gonzalez, Christopher J., Swaminathan, Karthik, Dhanwada, Nagu R., Muller, Silvia M., Wagner, Andreas, Sadasivam, Satish Kumar, Montoye, Robert K., Starke, William J., Zoellin, Christian G., Floyd, Michael S., Stuecheli, Jeffrey, Chandramoorthy, Nandhini, Wellman, John-David, Buyuktosunoglu, Alper, Pflanz, Matthias, Sinharoy, Balaram, Bose, Pradip

“…We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting…”
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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons by Seo, J., Brezzo, B., Liu, Y., Parker, B. D., Esser, S. K., Montoye, R. K., Rajendran, B., Tierno, J. A., Chang, L., Modha, D. S., Friedman, D. J.

“…Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the…”
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Demonstration of CAM and TCAM Using Phase Change Devices by Rajendran, B, Cheek, R W, Lastras, L A, Franceschini, M M, Breitwisch, M J, Schrott, A G, Jing Li, Montoye, R K, Chang, Leland, Chung Lam

“…We demonstrate novel designs for Content Addressable Memory (CAM) and Ternary CAM (TCAM) using Phase Change Memory (PCM) technology, which can potentially…”
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Stable SRAM cell design for the 32 nm node and beyond by Chang, L., Fried, D.M., Hergenrother, J., Sleight, J.W., Dennard, R.H., Montoye, R.K., Sekaric, L., McNab, S.J., Topol, A.W., Adams, C.D., Guarini, K.W., Haensch, W.

“…SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for…”
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Practical Strategies for Power-Efficient Computing Technologies : CIRCUIT TECHNOLOGY FOR ULTRA-LOW POWER (ULP) by CHANG, Leland, FRANK, David J, MONTOYE, Robert K, KOESTER, Steven J, JI, Brian L, COTEUS, Paul W, DENNARD, Robert H, HAENSCH, Wilfried

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A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation by Ditlow, G S, Montoye, R K, Storino, S N, Dance, S M, Ehrenreich, S, Fleischer, B M, Fox, T W, Holmes, K M, Mihara, J, Nakamura, Y, Onishi, S, Shearer, R, Wendel, D, Leland Chang

“…In multi-ported register files, memory cell size grows quadratically with the total number of ports due to wordline and bitline wiring. Reducing the number of…”
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Wide limited switch dynamic logic circuit implementations by Sivagnaname, J., Ngo, H.C., Nowka, K.J., Montoye, R.K., Brown, R.B.

“…Wide circuit implementation of limited switch dynamic logic (LSDL), a high performance logic circuit, with a modified pseudo-nMOS style load has been studied…”
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A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS by Leland Chang, Nakamura, Y., Montoye, R.K., Sawada, J., Martin, A.K., Kinoshita, K., Gebara, F.H., Agarwal, K.B., Acharyya, D.J., Haensch, W., Hosokawa, K., Jamsek, D.

“…A 32 kb subarray demonstrates practical implementation of a 65 nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows…”
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Second-generation RISC floating point with multiply-add fused by Hokenek, E., Montoye, R.K., Cook, P.W.

“…A 440000-transistor second-generation RISC (reduced instruction set computer) floating-point chip is described. The pipeline latency is only two cycles, and a…”
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Design-performance trade-offs in CMOS-domino logic by Oklobdzija, V.G., Montoye, R.K.

“…The authors present a study of the charge-sharing problem and its effect on the performance of CMOS-domino logic. Several solutions to the charge-sharing…”
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AREA-Time Efficient Addition in Charge Based Technology by Montoye, R.K.

“…Using the model developed by Mead and Conway for charge based technology, a methodology for the production of area-time efficient adders which imbeds the…”
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Controlled-load limited switch dynamic logic circuit by Sivagnaname, J., Ngo, H.C., Nowka, K.J., Montoye, R.K., Brown, R.B.

“…Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit…”
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A Practical Algorithm for the Solution of Triangular Systems on a Parallel Processing System by Montoye, R K, Lawrie, D H

“…An algorithm is presented for a more efficient and implementable solution of triangular systems on a parallel (SIMD) computer which requires 0(log (N)) fewer…”
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