Search Results - "MATSUTANI, H"

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  1. 1

    Effect of fiber length on the tensile strength of unidirectionally arrayed chopped strands by Taketa, I., Matsutani, H.

    Published in Advanced composite materials (02-01-2020)
    “…This study investigates the effect of fiber length on the tensile strength for discontinuous fiber composites. A composite with a staggered structure of fiber…”
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    Journal Article
  2. 2

    Prediction of tensile strength of discontinuous carbon fiber/polypropylene composite with fiber orientation distribution by Hashimoto, M., Okabe, T., Sasayama, T., Matsutani, H., Nishikawa, M.

    “…This study proposes the layer-wise method (LWM) as a new approach for predicting the tensile strength of discontinuous fiber-reinforced composites that have…”
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    Journal Article
  3. 3

    A study of stress concentrations around fiber breaks in unidirectional CF/epoxy composites using double-fiber fragmentation tests by Watanabe, J., Tanaka, F., Higuchi, R., Matsutani, H., Okuda, H., Okabe, T.

    Published in Advanced composite materials (02-11-2018)
    “…The prediction of tensile strength of unidirectional CF/epoxy composites requires appropriately determining the tensile strength distribution of carbon fibers…”
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    Journal Article
  4. 4

    Flowability of unidirectionally arrayed chopped strands in compression molding by Taketa, I., Okabe, T., Matsutani, H., Kitano, A.

    Published in Composites. Part B, Engineering (01-09-2011)
    “…This paper investigates the flowability of unidirectionally arrayed chopped strands (UACS) in compression molding of flat plates and rib structures. UACS is…”
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    Journal Article
  5. 5

    Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network by Matsutani, H., Koibuchi, M., Yamada, Y., Hsu, D.F., Amano, H.

    “…The topological explorations of on-chip networks are important for efficiently using their enormous wire resources for low-latency and high-throughput…”
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    Journal Article
  6. 6

    Layout-conscious random topologies for HPC off-chip interconnects by Koibuchi, M., Fujiwara, I., Matsutani, H., Casanova, H.

    “…As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Random network…”
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    Conference Proceeding
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    P1444 Occurrence and predictors of right ventricular dysfunction after pericardiocentesis by Matsutani, H, Amano, M, Izumi, C, Baba, M, Abe, R, Hashiwada, S, Kuwano, K, Shimada, M, Sakamoto, J, Miyake, M, Tamura, T, Matsuo, S

    “…Abstract Background—The changes in cardiac function that occur after pericardiocentesis are unclear.Purpose—This study was performed to assess right…”
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    Journal Article
  12. 12

    Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors by Matsutani, H., Koibuchi, M., Amano, H., Yoshinaga, T.

    Published in IEEE transactions on computers (01-06-2011)
    “…Multi and many-core applications are sensitive to interprocessor communication latencies, suggesting the need for low-latency on-chip networks. We propose a…”
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    Journal Article
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    Azimuthally controlled observation of heavy cosmic-ray primaries by means of the balloon-borne emulsion chamber by Kamioka, E., Hareyama, M., Ichimura, M., Ishihara, Y., Kobayashi, T., Komatsu, H., Kuramata, S., Maruguchi, K., Matsutani, H., Mihashi, A., Mito, H., Nakamura, T., Nanjo, H., Ouchi, T., Ozawa, T., Shibata, T., Sugimoto, H., Watanabe, Z.

    Published in Astroparticle physics (01-02-1997)
    “…We have exposed an emulsion chamber with an area of 1.22 m 2 on board of the balloon at an atmospheric depth of 8.9 g/cm 2 for 15.8 h, which has been…”
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    Journal Article
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    A case for random shortcut topologies for HPC interconnects by Koibuchi, M., Matsutani, H., Amano, H., Hsu, D. F., Casanova, H.

    “…As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern…”
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    Conference Proceeding
  17. 17

    Tightly-Coupled Multi-Layer Topologies for 3-D NoCs by Matsutani, H., Koibuchi, M., Amano, H.

    “…Three-dimensional network-on-chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for…”
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    Conference Proceeding
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    Prediction router: Yet another low latency on-chip router architecture by Matsutani, H., Koibuchi, M., Amano, H., Yoshinaga, T.

    “…Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core…”
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    Conference Proceeding
  20. 20

    An adaptive cryptographic accelerator for IPsec on dynamically reconfigurable processor by Hasegawa, Y., Abe, S., Matsutani, H., Amano, H., Anjo, K., Awashima, T.

    “…We propose a cryptographic accelerator for IPsec by using the NEC electronics' dynamically reconfigurable processor (DRP). In our system, an embedded processor…”
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    Conference Proceeding