Search Results - "MAN KIT TANG"

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  1. 1

    A 110-MHz/1-Mb synchronous TagRAM by Unekawa, Y., Kobayashi, T., Shirotori, T., Fujimoto, Y., Shimazawa, T., Nogami, K., Nakao, T., Sawada, K., Matsui, M., Sakurai, T., Man Kit Tang, Huffman, W.A.

    Published in IEEE journal of solid-state circuits (01-04-1994)
    “…A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation…”
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    Journal Article
  2. 2
  3. 3

    A 11O MHz/1 Mbit synchronous Tag RAM by Unekawa, Kobayashi, Shirotori, Fujimoto, Shimazawa, Nogami, Nakao, Sawada, Matsui, Sakurai, Man Kit Tang, Huffman

    Published in Symposium 1993 on VLSI Circuits (1993)
    “…The synchronous Tag RAM reported in this paper holds addresses and status bits of cached data and can be used to build a secondary cache system of up to…”
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    Conference Proceeding
  4. 4

    A 300 MIPS, 300 MFLOPS four-issue CMOS superscalar microprocessor by Ikumi, N., Tanaka, S., Sawada, K., Nagamatsu, M., Kondo, Y., Takayanagi, T., Minagawa, K., Akiba, H., Miyamoto, K., Hiruta, Y., Hsu, P., Rodman, P., Bratt, J., Man Kit Tang, Nofal, M., Joshi, C., Scanlon, J.

    “…A RISC CMOS superscalar microprocessor, operating at 75 MHz, executes up to four instructions per clock cycle, totalling 300M instructions per second. The chip…”
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    Conference Proceeding