Search Results - "Lu, Shengshuo"

  • Showing 1 - 7 results of 7
Refine Results
  1. 1

    A low power software-defined-radio baseband processor for the Internet of Things by Yajing Chen, Shengshuo Lu, Hun-Seok Kim, Blaauw, David, Dreslinski, Ronald G., Mudge, Trevor

    “…In this paper, we define a configurable Software Defined Radio (SDR) baseband processor design for the Internet of Things (IoT). We analyzed the fundamental…”
    Get full text
    Conference Proceeding Journal Article
  2. 2

    1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks by Shengshuo Lu, Zhengya Zhang, Papaefthymiou, Marios

    “…A 128-bit Advanced Encryption Standard (AES) core targeted for high-performance security applications is fabricated in a 65nm CMOS technology. A novel…”
    Get full text
    Conference Proceeding Journal Article
  3. 3

    Secure and Energy-Efficient Processors by Lu, Shengshuo

    Published 01-01-2017
    “…Security has become an essential part of digital information storage and processing. Both high-end and low-end applications, such as data centers and Internet…”
    Get full text
    Dissertation
  4. 4

    A programmable Galois Field processor for the Internet of Things by Chen, Yajing, Lu, Shengshuo, Fu, Cheng, Blaauw, David, Dreslinski, Ronald, Mudge, Trevor, Kim, Hun-Seok

    “…This paper investigates the feasibility of a unified processor architecture to enable error coding flexibility and secure communication in low power Internet…”
    Get full text
    Conference Proceeding
  5. 5

    A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices by Shengshuo Lu, Zhengya Zhang, Papaefthymiou, Marios

    “…An AES core designed for low-cost and energy-efficient IoT security applications is fabricated in a 65nm CMOS technology. A novel Dual-Rail Flush Logic (DRFL)…”
    Get full text
    Conference Proceeding
  6. 6

    A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh by Shengshuo Lu, Zhengya Zhang, Papaefthymiou, Marios

    “…This paper presents an ultra-high-performance neural network engine fabricated in a 65nm CMOS technology. The 0.9mm 2 core relies on an energy-efficient…”
    Get full text
    Conference Proceeding
  7. 7

    Rethinking Numerical Representations for Deep Neural Networks by Hill, Parker, Zamirai, Babak, Lu, Shengshuo, Chao, Yu-Wei, Laurenzano, Michael, Samadi, Mehrzad, Papaefthymiou, Marios, Mahlke, Scott, Wenisch, Thomas, Deng, Jia, Tang, Lingjia, Mars, Jason

    Published 07-08-2018
    “…With ever-increasing computational demand for deep learning, it is critical to investigate the implications of the numeric representation and precision of DNN…”
    Get full text
    Journal Article