Search Results - "Low, Jeremy Yung Shern"

Erratum to “Efficient VLSI Implementation of Scaling of Signed Integer in RNS {}” [Oct 13 1936-1940] by Tay, Thian Fatt, Chang, Chip-Hong, Low, Jeremy Yung Shern

“…The authors would like to point out the following correction in the total power consumptions recorded in Table IV of the published article [1] . The total…”
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Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set [Formula Omitted] by Chang, Chip-Hong, Low, Jeremy Yung Shern

“…Scaling in RNS has always been conceived as a performance bottleneck similar to the residue-to-binary conversion problem due to the inefficient intermodulo…”
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Erratum to "Efficient VLSI Implementation of 2^ Scaling of Signed Integer in RNS -1 , 2^ , 2^ +1$ }" [Oct 13 1936-1940] by Tay, Thian Fatt, Chang, Chip-Hong, Low, Jeremy Yung Shern

“…The authors would like to point out the following correction in the total power consumptions recorded in Table IV of the published article <xref…”
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An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS by Do Anh-Tuan, Low, Jeremy Yung Shern, Low, Joshua Yung Lih, Zhi-Hui Kong, Xiaoliang Tan, Kiat-Seng Yeo

“…Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Due to parameter fluctuations in…”
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A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli by Low, Jeremy Yung Shern, Chip-Hong Chang

“…Recent analyses demonstrate that operations in some bases of Residue Number System (RNS) exhibit higher resiliency to process variations than in normal binary…”
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Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n ― 1, 2n, 2n + 1} by CHANG, Chip-Hong, JEREMY YUNG SHERN LOW

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Efficient VLSI Implementation of [Formula Omitted] Scaling of Signed Integer in RNS [Formula Omitted] by Tay, Thian Fatt, Chang, Chip-Hong, Low, Jeremy Yung Shern

“…Scaling is a problematic operation in residue number system (RNS) but a necessary evil in implementing many digital signal processing algorithms for which RNS…”
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Efficient VLSI Implementation of 2 n Scaling of Signed Integer in RNS { 2 n - 1 , 2 n ,2 n + 1 } by Tay, Thian Fatt, Chang, Chip-Hong, Low, Jeremy Yung Shern

“…Scaling is a problematic operation in residue number system (RNS) but a necessary evil in implementing many digital signal processing algorithms for which RNS…”
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Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM by Anh-Tuan Do, Zhi-Hui Kong, Kiat-Seng Yeo, Low, Jeremy Yung Shern

“…A new current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving…”
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Efficient VLSI Implementation of 2^} Scaling of Signed Integer in RNS -1, 2^,2^+1 by Tay, Thian Fatt, Chip-Hong Chang, Low, Jeremy Yung Shern

“…Scaling is a problematic operation in residue number system (RNS) but a necessary evil in implementing many digital signal processing algorithms for which RNS…”
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Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set \ - 1, 2^, 2^ + 1 by Chip-Hong Chang, Low, J. Y. S.

“…Scaling in RNS has always been conceived as a performance bottleneck similar to the residue-to-binary conversion problem due to the inefficient intermodulo…”
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A fast and compact circuit for integer square root computation based on Mitchell logarithmic method by Low, Joshua Yung Lih, Jong, Ching Chuen, Low, Jeremy Yung Shern, Tay, Thian Fatt, Chang, Chip-Hong

“…A novel non-iterative circuit for computing integer square root based on logarithm is proposed in the paper. Mitchell's methods are used for the logarithmic…”
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A new RNS scaler for by Low, J. Y. S., Chip Hong Chang

“…This paper presents an efficient RNS scaling algorithm for the balanced special moduli set {2 n -1, 2 n , 2 n +1}. By exploiting the relationship between the…”
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A signed integer programmable power-of-two scaler for RNS by Low, Jeremy Yung Shern, Thian Fatt Tay, Chip-Hong Chang

“…Scaling is used for wordlength reduction in many DSP algorithms. Variable scaler provides greater flexibility than fixed scaler and allows for more efficient…”
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A novel counter-based low complexity inner-product architecture for high speed inputs by Meher, M R, Ching-Chuen Jong, Chip-Hong Chang, Low, J Y S

“…This paper presents a new methodology of multiplierless implementation of inner-product computation. The inner-product computation is decomposed to form an…”
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A unified RNS scaler with dual scaling constants by Low, Jeremy Yung Shern, Tay, Thian Fatt, Chip-Hong Chang

“…Scaling is often used to prevent overflow in digital signal processing (DSP). Unfortunately, scaling in residue number system (RNS) consumes significant…”
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Performance analysis of different special moduli sets for RNS-based inner product step processor by Bin Cao, Low, Jeremy Yung Shern, Chip-Hong Chang, Srikanthan, T

“…This paper studies the performance of RNS-based inner product step processor of different special moduli sets. The processor is generic with programmable…”
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A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion by Tang, H., Low, J. Y. L., Low, J. Y. S., Siek, L., Ching Chuen Jong, Chip-Hong Chang

“…This paper presents a new 16-bit analog-to-residue converter (ARC) for a three moduli set {2 6 -1, 2 6 , 2 6 +1} RNS with a dynamic range of 18 bits. Based on…”
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An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving by Anh Tuan Do, Kiat Seng Yeo, Low, Jeremy Yung Shern, Low, Joshua Yung Lih, Zhi Hui Kong

“…Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Several 8T and 10T cell designs…”
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A full current-mode sense amplifier for low-power SRAM applications by Anh-Tuan Do, Low Yung Shern, J., Zhi-Hui Kong, Kiat-Seng Yeo, Low Yung Lih, J.

“…A full current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving…”
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