Search Results - "Louveau, Olivier"
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1
Impact of patterning and ashing on electrical properties and reliability of interconnects in porous SiOCH ultra low-k dielectric materials
Published in Microelectronic engineering (2005)“…In this study, a PECVD porous SiOCH dielectric with k = 2.4 is integrated in a Cu single damascene architecture. The main issue investigated is the low k…”
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Journal Article -
2
Three dimensional chip stacking using a wafer-to-wafer integration
Published in 2007 IEEE International Interconnect Technology Conferencee (01-06-2007)“…A three-dimensional (3D) wafer-to-wafer integration technology has been developed using face-to-face dielectric wafer bonding, followed by wafer thinning and…”
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Conference Proceeding