Search Results - "Lorant, C."

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails by Veloso, A., Jourdain, A., Radisic, D., Chen, R., Arutchelvan, G., O'Sullivan, B., Arimura, H., Stucchi, M., De Keersgieter, A., Hosseini, M., Hopf, T., D'have, K., Wang, S., Dupuy, E., Mannaert, G., Vandersmissen, K., Iacovo, S., Marien, P., Choudhury, S., Schleicher, F., Sebaai, F., Oniki, Y., Zhou, X., Gupta, A., Schram, T., Briggs, B., Lorant, C., Rosseel, E., Hikavyy, A., Loo, R., Geypen, J., Batuk, D., Martinez, G. T., Soulie, J. P., Devriendt, K., Chan, B. T., Demuynck, S., Hiblot, G., Van der Plas, G., Ryckaert, J., Beyer, G., Litta, E. Dentoni, Beyne, E., Horiguchi, N.

“…We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight…”
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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails by Veloso, A., Jourdain, A., Radisic, D., Chen, R., Arutchelvan, G., O'Sullivan, B., Arimura, H., Stucchi, M., Keersgieter, A. De, Hosseini, M., Hopf, T., D'Have, K., Wang, S., Dupuy, E., Mannaert, G., Vandersmissen, K., Iacovo, S., Marien, P., Choudhury, S., Schleicher, F., Sebaai, F., Oniki, Y., Zhou, X., Gupta, A., Schram, T., Briggs, B., Lorant, C., Rosseel, E., Hikavyy, A., Loo, R., Geypen, J., Batuk, D., Martinez, G. T., Soulie, J. P., Devriendt, K., Chan, B. T., Demuynck, S., Hiblot, G., der Plas, G. Van, Ryckaert, J., Beyer, G., Litta, E. Dentoni, Beyne, E., Horiguchi, N.

“…We report on scaled finFETs with a novel routing scheme enabling connection via buried power rails (BPR) from both wafer sides, with tight variability/matching…”
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Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node by Gupta, A., Mertens, H., Tao, Z., Demuynck, S., Bommels, J., Arutchelvan, G., Devriendt, K., Pedreira, O. Varela, Ritzenthaler, R., Wang, S., Radisic, D., Kenis, K., Teugels, L., Sebaai, F., Lorant, C., Jourdan, N., Chan, B. T., Zahedmanesh, H., Subramanian, S., Schleicher, F., Hopf, T., Peter, A., Rassoul, N., Debruyn, H., Demonie, I., Siew, Y., Chiarella, T., Briggs, B., Zhou, D., Rosseel, E., De Keersgieter, A., Capogreco, E., Litta, E. Dentoni, Boccardi, G., Baudot, S., Mannaert, G., Bontemps, N., Sepulveda, A., Mertens, S., Kim, M. S., Dupuy, E., Vandersmissen, K., Paolillo, S., Yakimets, D., Chehab, B., Favia, P., Drijbooms, C., Cousserier, J., Jaysankar, M., Lazzarino, F., Morin, P., Sanchez, E., Mitard, J., Wilson, C., Holsteyns, F., Tokei, Z., Horiguchi, N.

“…Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of…”
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The kinetics of SARS-CoV-2 viremia in COVID-19 patients receiving remdesivir by Krifors, Anders, Karlsson, Linda, Ekman, Martin, Lorant, Camilla, Skorup, Paul

“…Detection of SARS-CoV-2 RNA in serum, viremia, has been linked to disease severity and outcome. The kinetics of viremia in patients receiving remdesivir has…”
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Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond by Gupta, A., Pedreira, O. Varela, Tao, Z., Mertens, H., Radisic, D., Jourdan, N., Devriendt, K., Heylen, N., Wang, S., Chehab, B., Jang, D., Hellings, G., Sebaai, F., Lorant, C., Teugels, L., Peter, A., Chan, BT, Schleicher, F., Demonie, I., Marien, P., Sepulveda, A., Richard, O., Nagesh, N., Lesniewska, A., Lazzarino, F., Ryckaert, J., Morin, P., Altamirano-Sanchez, E., Murdoch, G., Bommels, J., Demuynck, S., Na, M. H, Tokei, Z., Biesemans, S., Litta, E. Dentoni, Horiguchi, N.

“…This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate pitch (CPP), and W and Ru-BPR and Ru-…”
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Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm Node by Vega-Gonzalez, V., Bekaert, J., Kesters, E., Le, Q. T., Lorant, C., Varela P., O., Teugels, L., Heylen, N., El-Mekki, Z., van der Veen, M., Webers, T., Wilson, C. J., Vats, H., Rynders, L., Cupak, M., Uk-Lee, J., Drissi, Y., Halipre, L., Charley, A.-L., Verdonck, P., Witters, T., Gompel, S. V., Briggs, B., Kimura, Y., Jourdan, N., Ciofi, I., Gupta, A., Contino, A., Boccardi, G., Lariviere, S., Dupas, L., De-Wachter, B., Vancoille, E., Decoster, S., Lazzarino, F., Ercken, M, Debacker, P., Kim, R., Trivkovic, D., Croes, K., Leray, P., Dillemans, L., Chen, Y.-F., Tokei, Z., Versluijs, J., Lesniewska, A., Paolillo, S., Baert, R., Puliyalil, H.

“…The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full…”
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Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium by Vega-Gonzalez, V., Puliyalil, H., Versluijs, J., Lesniewska, A., Varela-Pereira, O., Baert, R., Paolillo, S., Decoster, S., Schleicher, F., Montero, D., Bekaert, J., Kesters, E., Le, Q. T., Lorant, C., Teugels, L., Heylen, N., Jourdan, N., El-Mekki, Z., van der Veen, M., Ciofi, I., Briggs, B., Heijlen, J., Dupas, L., De-Wachter, B., Vancoille, E., Webers, T., Vats, H., Rynders, L., Cupak, M., Uk-Lee, J., Drissi, Y., Halipre, L., Charley, A.-L., Verdonck, P., Witters, T., Gompel, S. V., Kimura, Y., Demonie, I., Lazzarino, F., Ercken, M, Kim, R., Trivkovic, D., Croes, K., Leray, P., Jaysankar, M., Wilson, C., Muroch, G., Tokei, Z.

“…The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated…”
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12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices by Kim, M.-S., Harada, N., Kikuchi, Y., Boemmels, J., Mitard, J., Huynh-Bao, T., Matagne, P., Tao, Z., Li, W., Devriendt, K., Ragnarsson, L.-A., Lorant, C., Sebaai, F., Porret, C., Rosseel, E., Dangol, A., Batuk, D., Martinez-Alanis, G., Geypen, J., Jourdan, N., Sepulveda, A., Puliyalil, H., Jamieson, G., van der Veen, M., Teugels, L., El-Mekki, Z., Altamirano-Sanchez, E., Li, Y., Nakamura, H., Mocuta, D., Masuoka, F.

“…For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with 0.0205\ \mu \text{m}^{2} unit…”
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DTCO and TCAD for a 12 Layer-EUV Ultra-Scaled Surrounding Gate Transistor 6T-SRAM by Matagne, P., Nakamura, H., Kim, M.-S., Kikuchi, Y., Huynh-Bao, T., Tao, Z., Li, W., Devriendt, K., Ragnarsson, L.-A., Boemmels, J., Mallik, A., Altamirano-Sachez, E., Sebaai, F., Lorant, C., Jourdan, N., Porret, C., Mocuta, D., Harada, N., Masuoka, F.

“…A flow, module steps and key structural elements enabling a surrounding gate transistor (SGT) based 6T-SRAM with 50nm pillar pitch and 0.0205 um2 are…”
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Variance of a product of powers of independent random variables with small deviations from their means by Lorant, C.R.

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