Search Results - "Loiko, K"

SiGe-Channel Confinement Effects for Short-Channel PFETs With Nonbandedge Gate Workfunctions by Winstead, B., Taylor, W.J., Verret, E., Loiko, K., Tekleab, D., Capasso, C., Foisy, M., Samavedam, S.B.

“…Thin SiGe-channel confinement is found to provide significant control of the short channel effects typically associated with nonbandedge gate electrodes, in an…”
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A critical re-examination of body-bias on the soft error rate and single-event latch-up in automotive SRAMs by Mahatme, N. N., Min, B., Loiko, K.

“…Body-biasing is commonly used to regulate power/performance for modern integrated circuits. However, it has an additional soft error rate (SER) and single…”
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Highly Optimized Nanocrystal-Based Split Gate Flash for High Performance and Low Power Microcontroller Applications by Yater, J, Hong, C, Kang, S.-T, Kolar, D, Min, B, Shen, J, Chindalore, G, Loiko, K, Winstead, B, Williams, S, Gasquet, H, Suhail, M, Broeker, K, Lepore, E, Hardell, A, Malloch, W, Syzdek, R, Chen, Y, Ju, Y, Kumarasamy, S, Liu, H, Lei, L, Indajang, B

“…We show a 90nm nanocrystal-based split gate embedded flash memory that is able to meet the speed, endurance and reliability requirements for 32-bit…”
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Multiple rings formation in cascaded conical refraction by Turpin, A, Kalkandjiev, Yu. V. Loiko. T. K, Mompart, J

“…Optics Letters, Vol. 38, Issue 9, pp. 1455-1457 (2013) When a light beam passes through a cascade of biaxial crystals with aligned optic axes, the resulting…”
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First-ever high-performance, low-power 32-bit microcontrollers with embedded nanocrystal flash and enhanced EEPROM memories by Yater, J., Kang, S.-T, Hong, C. M., Min, B., Kolar, D., Loiko, K., Shen, J., Winstead, B., Gasquet, H., Mohammed, S., Hardell, A., Malloch, W., Cook, B., Syzdek, R., Jarrar, A., Feddeler, J., Baker, K., Chang, K. M., Herrin, S., Parks, R., Chindalore, G.

“…We present the first-ever commercially available microcontroller families built with innovative split-gate based NOR flash memory that uses silicon…”
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A predictive semi-analytical threshold voltage model for deep-submicron MOSFET's by Lim, K.Y., Zhou, X., Lim, D., Zu, Y., Ho, H.M., Loiko, K., Lau, C.K., Tse, M.S., Choo, S.C.

“…A compact threshold voltage model is developed for the prediction of deep-submicron MOSFETs scaling characteristic based on comprehensive 2-D device…”
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Stress Sensitivity of PMOSFET Under High Mechanical Stress by Tekleab, D., Adams, V., Loiko, K., Winstead, B., Parsons, S., Grudowski, P., Foisy, M.

“…Using PMOSFETs with a range of built-in process induced stress and four-point bending characterization, we present evidence that the stress response of…”
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Multi-Layer Model for Stressor Film Deposition by Loiko, K.V., Adams, V., Tekleab, D., Winstead, B., Bo, X.-Z., Grudowski, P., Goktepeli, S., Filipiak, S., Goolsby, B., Kolagunta, V., Foisy, M.C.

“…Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of…”
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An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing by Grudowski, P., Dhandapani, V., Zollner, S., Goedeke, D., Loiko, K., Tekleab, D., Adams, V., Spencer, G., Desjardins, H., Prabhu, L., Garcia, R., Foisy, M., Theodore, D., Bauer, M., Weeks, D., Thomas, S., Thean, A., White, B.

“…We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to…”
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Modeling and Simulation of Poly-Space Effects in Uniaxially-Strained Etch Stop Layer Stressors by Lixin Ge, Adams, V., Loiko, K., Tekleab, D., Xiang-Zheng Bo, Foisy, M., Kolagunta, V., Veeraraghavan, S.

“…We develop, for the first time, a compact and scalable model to account for the poly-space effects (PSEs) in uniaxially-strained etch stop layer (ESL)…”
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1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations by Grudowski, P., Adams, V., Bo, X.-Z., Loiko, K., Filipiak, S., Hackenberg, J., Jahanbani, M., Azrak, M., Goktepeli, S., Shroff, M., Liang, W.-J., Lian, S., Kolagunta, V., Cave, N., Wu, C.-H., Foisy, M., Tuan, H., Cheek, J.

“…We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry…”
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Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors by Xiang-Zheng Bo, Grudowski, P., Adams, V., Loiko, K., Tekleab, D., Filipiak, S., Hackenberg, J., Kolagunta, V., Foisy, M., Li-Te Lin, Fung, K.H., Chi-Hsi Wu, Hsiao-Chin Tuan, Cheek, J.

“…We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors…”
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High Performance Nanocrystal Based Embedded Flash Microcontrollers with Exceptional Endurance and Nanocrystal Scaling Capability by Sung-Taeg Kang, Winstead, B., Yater, J., Suhail, M., Zhang, G., Hong, C.-M, Gasquet, H., Kolar, D., Shen, J., Min, B., Loiko, K., Hardell, A., LePore, E., Parks, R., Syzdek, R., Williams, S., Malloch, W., Chindalore, G., Chen, Y., Shao, Y., Huajun, L., Louis, L., Chwa, S.

“…In this paper, we present the first-ever commercially available embedded Microcontrollers built on 90nm-node with silicon nanocrystal memories that has…”
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16Mb Split Gate Flash Memory with Improved Process Window by Yater, J., Suhail, M., Kang, S.-T., Shen, J., Hong, C., Merchant, T., Gasquet, R.R.H., Loiko, K., Winstead, B., Williams, S., Rossow, M., Malloch, W., Syzdek, R., Chindalore, G.

“…This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for…”
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Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS by Taylor, W.J., Capasso, C., Min, B., Winstead, B., Verret, E., Loiko, K., Gilmer, D., Hegde, R.I., Schaeffer, J., Luckowski, E., Martinez, A., Raymond, M., Happ, C., Triyoso, D.H., Kalpat, S., Haggag, A., Roan, D., Nguyen, J.-Y., La, L. B., Hebert, L., Smith, J., Jovanovic, D., Burnett, D., Foisy, M., Cave, N., Tobin, P.J., Samavedam, S.B., White, B.E., Venkatesan, S.

“…We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm…”
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Influence of plasma induced damage during active etch on silicon defect generation by Nallapati, G., Loiko, K.V.

“…The role of plasma induced damage during active nitride etch in silicon defect generation was investigated. A correlation was established between the overetch…”
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Methodology for ULSI LOCOS isolation built-in reliability analysis by Loiko, K.V., Peidous, I.V., Hok-Min Ho, Quek, E.K.B., Lim, D.H.Y.

“…The results of studying the mechanisms of CMOS ULSI LOCOS isolation failures and an effective approach to qualifying the technological processes of isolation…”
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Functional state of the stomach after gastrectomy and vagotomy and the ways of improving the results of surgical treatment of peptic ulcer by Khoromskiĭ, L N, Benedikt, V V, Loĭko, I K, Kit, O N, Pustovoĭt, G T

“…A complex examination of 286 patients was performed after gastric resection by the method of Hofmeister-Finsterer, 64 patients after truncal vagotomy with…”
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Right heart function and changes in the lymphatic system of serous membranes in pulmonary arterial hypertension by Loĭko, I K

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Function of the heart and changes in the lymphatic bed of the serous membranes of the thorax and abdominal cavity after resection of the lungs (in experiments) by Loĭko, I K, Loĭko, V V

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