Search Results - "Lohana, Aditya"

ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems by Nambi, Suresh, Ullah, Salim, Sahoo, Siva Satyendra, Lohana, Aditya, Merchant, Farhad, Kumar, Akash

“…The high computational complexity, memory footprints, and energy requirements of machine learning models, such as Artificial Neural Networks (ANNs), hinder…”
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Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization by Rai, Shubham, Neto, Walter Lau, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Yi, Qingyang, Fujita, Masahiro, Manske, Guilherme B., Pontes, Matheus F., da Rosa, Leomar S., de Aguiar, Marilton S., Butzen, Paulo F., Chien, Po-Chun, Huang, Yu-Shan, Wang, Hoa-Ren, Jiang, Jie-Hong R., Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z., de Abreu, Brunno A., de Souza Campos, Isac, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T., Grellert, Mateus, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O., Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Gaillardon, Pierre-Emmanuel, Mishchenko, Alan, Chatterjee, Satrajit

“…Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area…”
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ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems by Nambi, Suresh, Ullah, Salim, Lohana, Aditya, Sahoo, Siva Satyendra, Merchant, Farhad, Kumar, Akash

“…The recent advances in machine learning, in general, and Artificial Neural Networks (ANN), in particular, has made smart embedded systems an attractive option…”
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Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization by Rai, Shubham, Neto, Walter Lau, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Fujita, Qingyang Yi Masahiro, Manske, Guilherme B, Pontes, Matheus F, Junior, Leomar S. da Rosa, de Aguiar, Marilton S, Butzen, Paulo F, Chien, Po-Chun, Huang, Yu-Shan, Wang, Hoa-Ren, Jiang, Jie-Hong R, Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z, de Abreu, Brunno A, Campos, Isac de Souza, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T, Grellert, Mateus, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O, Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Gaillardon, Pierre-Emmanuel, Mishchenko, Alan, Chatterjee, Satrajit

“…Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area…”
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Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy by Lohana, Aditya, Rupani, Ansh, Rai, Shubham, Kumar, Akash

“…This article introduces a low-communication-overhead technique targeted toward federated learning systems using additively homomorphic encryption…”
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