Search Results - "Loghi, Mirko"

Reducing the spike rate of deep spiking neural networks based on time-encoding by Fontanini, Riccardo, Pilotto, Alessandro, Esseni, David, Loghi, Mirko

“…A primary objective of Spiking Neural Networks is a very energy-efficient computation. To achieve this target, a small spike rate is of course very beneficial…”
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Modeling and Design of FTJs as Multi-Level Low Energy Memristors for Neuromorphic Computing by Fontanini, Riccardo, Segatto, Mattia, Massarotto, Marco, Specogna, Ruben, Driussi, Francesco, Loghi, Mirko, Esseni, David Esseni

“…An in-house modeling framework for Ferroelectric Tunnelling Junctions (FTJ) is here presented in details. After a precise calibration again experiments, the…”
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Dynamic Indexing: Leakage-Aging Co-Optimization for Caches by Calimera, Andrea, Loghi, Mirko, Macii, Enrico, Poncino, Massimo

“…Traditional implementations of low-power states based on voltage scaling or power gating have been shown to have a beneficial effect on the aging phenomena…”
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Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation by Mahmood, Haroon, Loghi, Mirko, Poncino, Massimo, Macii, Enrico

“…Aging of transistors can adversely impact the long-term reliability of devices in subnanometric technologies. Without any countermeasure, the first component…”
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Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking by Loghi, Mirko, Golubeva, Olga, Macii, Enrico, Poncino, Massimo

“…Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its…”
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A Portable 3-D Imaging FMCW MIMO Radar Demonstrator With a 24\times 24 Antenna Array for Medium-Range Applications by Ganis, Alexander, Miralles Navarro, Enric, Schoenlinner, Bernhard, Prechtel, Ulrich, Meusling, Askold, Heller, Christoph, Spreng, Thomas, Mietzner, Jan, Krimmer, Christian, Haeberle, Babette, Lutz, Steffen, Loghi, Mirko, Belenguer, Angel, Esteban, Hector, Ziegler, Volker

“…Multiple-input multiple-output (MIMO) radars have been shown to improve target detection for surveillance applications thanks to their proven high-performance…”
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Dynamic indexing: Concurrent leakage and aging optimization for caches by Calimera, Andrea, Loghi, Mirko, Macii, Enrico, Poncino, Massimo

“…Previous works have shown that the traditional implementations of power management (i.e., using power gating or voltage scaling) can also mitigate the aging…”
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Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support by Poletti, Francesco, Poggiali, Antonio, Bertozzi, Davide, Benini, Luca, Marchal, Pol, Loghi, Mirko, Poncino, Massimo

“…In today's multiprocessor SoCs (MPSoCs), parallel programming models are needed to fully exploit hardware capabilities and to achieve the 100 Gops/W energy…”
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Application-specific memory partitioning for joint energy and lifetime optimization by Mahmood, Haroon, Poncino, Massimo, Loghi, Mirko, Macii, Enrico

“…Power management of caches based on turning idle cache lines into a low-energy state is also beneficial for the aging effects caused by Negative Bias…”
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Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching by Loghi, M., Azzoni, P., Poncino, M.

“…We propose a novel energy-efficient cache architecture based on a matching mechanism that uses a reduced number of tag bits. The idea behind the proposed…”
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Low-cost jamming system against small drones using a 3D MIMO radar based tracking by Multerer, Thomas, Ganis, Alexander, Prechtel, Ulrich, Miralles, Enric, Meusling, Askold, Mietzner, Jan, Vossiek, Martin, Loghi, Mirko, Ziegler, Volker

“…This paper presents an anti-drone system which consists of a 3D Frequency Modulated Continuous Wave (FMCW) Multiple Input Multiple Output (MIMO) radar and a…”
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SystemC co-simulation for core-based embedded systems by Fummi, Franco, Loghi, Mirko, Perbellini, Giovanni, Poncino, Massimo

“…SystemC is becoming the reference language for hardware description in EDA community. It is suitable for describing hardware at several abstraction levels, and…”
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Application-specific memory partitioning for joint energy and lifetime optimization by Mahmood, H., Poncino, M., Loghi, M., Macii, E.

“…Power management of caches based on turning idle cache lines into a low-energy state is also beneficial for the aging effects caused by Negative Bias…”
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Analyzing on-chip communication in a MPSoC environment by Loghi, M., Angiolini, F., Bertozzi, D., Benini, L., Zafalon, R.

“…This work focuses on communication architecture analysis for multi-processor systems-on-chips (MPSoCs), and it leverages a SystemC-based platform to simulate a…”
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Architectural leakage-aware management of partitioned scratchpad memories by Golubeva, Olga, Loghi, Mirko, Poncino, Massimo, Macii, Enrico

“…Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its…”
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Modelling and design of FTJs as high reading-impedance synaptic devices by Fontanini, Riccardo, Massarotto, Marco, Specogna, Ruben, Driussi, Francesco, Loghi, Mirko, Esseni, David

“…We present an in-house modelling framework for Ferroelectric Tunnelling Junctions (FTJ), and an insightful study of the design of FTJs as synaptic devices…”
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Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies by Esseni, David, Fontanini, Riccardo, Lizzit, Daniel, Massarotto, Marco, Driussi, Francesco, Loghi, Mirko

“…The technological exploitation of ferroelectricity in CMOS electron devices offers new design opportunities, but also significant challenges from an…”
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Synchronization-driven dynamic speed scaling for MPSoCs by Loghi, Mirko, Poncino, Massimo, Benini, Luca

“…Equalizing the ratios between workloads and speeds of processing elements provides the optimal speed allocation. Based on that principle, this work describes a…”
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Architectural Leakage-Aware Management of Partitioned Scratchpad Memories by Golubeva, O., Loghi, M., Poncino, M., Macii, E.

“…Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its…”
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Locality-driven architectural cache sub-banking for leakage energy reduction by Golubeva, O, Loghi, M, Macii, E, Poncino, M

“…In most processors, caches account for the largest fraction of onchip transistors, thus being a primary candidate for tackling the leakage problem. Existing…”
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