Search Results - "Loan, Sajad A."

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  1. 1

    Novel carbon nanotube field effect transistor based dual output second‐generation current conveyor: Design and applications by Jogad, Seema, Loan, Sajad A., Afzal, Neelofer

    “…In this work, we propose, design and simulate a new configuration of Class AB dual output (DO) second‐generation current conveyor (DO‐CCII). Two versions of…”
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    Journal Article
  2. 2

    CNTFET based comparators: design, simulation and comparative analysis by Jogad, Seema, Akhoon, M. Saqib, Loan, Sajad A.

    “…In this work, we design and simulate carbon nanotube field effect transistor (CNTFET) based open-loop and dynamic comparators and compared the performance with…”
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  3. 3

    A Uni-gate vertical power MOSFET with improved figure of Merits: Design and analysis by Nigar, Hafsa, Alkhammash, Hend I., Qamar, Shamimul, Loan, Sajad A

    Published in Alexandria engineering journal (15-03-2023)
    “…In this paper, we propose and analyze a single buried gate power MOSFET structure. The structure uses single gate buried under the source and channel region…”
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  4. 4

    Electrostatically Doped DSL Schottky Barrier MOSFET on SOI for Low Power Applications by Bashir, Faisal, Alharbi, Abdullah G., Loan, Sajad A.

    “…In this paper, we propose and simulate a novel Schottky barrier MOSFET (SB-MOSFET) with improved performance in comparison to the conventional SB-MOSFET. The…”
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  5. 5

    A high performance gate engineered charge plasma based tunnel field effect transistor by Bashir, Faisal, Loan, Sajad A., Rafat, M., Alamoud, Abdul Rehman M., Abbasi, Shuja A.

    Published in Journal of computational electronics (01-06-2015)
    “…In this paper, we propose a new gate engineered dopingless tunnel field effect transistor (GEDL-TFET). GEDL-TFET has double gate and uses metals of different…”
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  6. 6

    Electrostatically-Doped Hetero-Barrier Tunnel Field Effect Transistor: Design and Investigation by Ehteshamuddin, M., Alharbi, Abdullah G., Loan, Sajad A.

    Published in IEEE access (2018)
    “…In this paper, an electrostatically-doped hetero-barrier tunnel-field-effect-transistor (ED-Het-TFET) based on stepped broken-gap (type-III) is simulated,…”
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  7. 7

    Drain-Engineered TFET With Fully Suppressed Ambipolarity for High-Frequency Application by Uddin Shaikh, Mohd Rizwan, Loan, Sajad A

    Published in IEEE transactions on electron devices (01-04-2019)
    “…In this paper, we propose and simulate a novel drain-engineered structure of a quadruple-gate tunnel field-effect transistor (TFET). The proposed device…”
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  8. 8

    Insights Into the Impact of Pocket and Source Elevation in Vertical Gate Elevated Source Tunnel FET Structures by Ashita, Loan, Sajad A., Rafat, Mohammad

    Published in IEEE transactions on electron devices (01-01-2019)
    “…In this paper, we investigate a vertical gate-based elevated tunnel source (TS) FET structure with and without a vertical n+ pocket and compare its performance…”
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  9. 9

    Dielectrically Modulated Source-Engineered Charge-Plasma-Based Schottky-FET as a Label-Free Biosensor by Hafiz, Syed Adeebul, Iltesha, Ehteshamuddin, M., Loan, Sajad A.

    Published in IEEE transactions on electron devices (01-04-2019)
    “…In this paper, we propose and simulate a charge-plasma (CP)-based dielectrically modulated (DM) source-engineered Schottky barrier field-effect transistor…”
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  10. 10
  11. 11

    Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation by Khan, Anam, Loan, Sajad A.

    Published in SILICON (01-05-2021)
    “…In this paper, we propose and simulate a novel double gate tunnel field effect transistor (DG-TFET) employing a metallic drain and a gate-drain underlap. The…”
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  12. 12

    CNTFET based 4-bit thermometer current steering digital to analog converter: design and analysis by Mujumdar, Suvarna, Loan, Sajad A., Afzal, Nelofer

    “…In this work, we design and simulate a 4-bit Thermometer architecture based Current Steering Digital to Analog Converter (TCS-DAC). Two versions of TCS-DAC…”
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  13. 13

    A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI by Bashir, Faisal, Loan, Sajad A., Rafat, Mohd, Alamoud, Abdul Rahman M., Abbasi, Shuja A.

    Published in IEEE transactions on electron devices (01-10-2015)
    “…In this paper, we address an important issue of low ON current in a Schottky barrier (SB) MOSFET by proposing a novel structure of Schottky MOSFET on silicon…”
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  14. 14

    Germanium pocket based tunnel FET with underlap: design and simulation by Khan, Anam, Alharbi, Abdullah G., Loan, Sajad A.

    “…Analysis has been carried out to check and study the working of a novel pocketed version of TFET in comparison to a conventional TFET. We have proposed a…”
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    Journal Article
  15. 15

    A Charge Plasma Based Dual Buried Gates Power MOSFET with Improved Figure of Merits by Nigar, Hafsa, Alkhammash, Hend I., Loan, Sajad A.

    Published in SILICON (01-07-2024)
    “…In this work, we design and simulate a high performance electrostatically doped dual buried gates power MOSFET (EDDBGP-MOS) structure. The novelty of the…”
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  16. 16

    CNTFET based class AB current conveyor II: Design, analysis and waveform generator applications by Jogad, Seema, Loan, Sajad A., Afzal, Neelofer, Alharbi, Abdullah G.

    “…In this work, we design and simulate a new class AB second generation current conveyor (CCII) employing 32 nm technology node carbon nanotube field effect…”
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  17. 17

    Investigating a Dual MOSCAP Variant of Line-TFET With Improved Vertical Tunneling Incorporating FIQC Effect by Ehteshamuddin, M., Loan, Sajad A., Alharbi, Abdullah. G., Alamoud, Abdulrahman M., Rafat, M.

    Published in IEEE transactions on electron devices (01-11-2019)
    “…In this article, we investigate a variant of the line-tunnel FET employing dual MOS-capacitor (MOSCAP) extensions incorporating field-induced quantum…”
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    Journal Article
  18. 18

    Pseudo Split Gate In0.53Ga0.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis by Haris, Mohd, Loan, Sajad A., Mainuddin

    “…In this work, we present the design and simulation of a novel structure of In0.53Ga0.43As/InP based hetero junction tunnel field effect transistor (HTFET). The…”
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  19. 19

    CNTFET‐based active grounded inductor using positive and negative current conveyors and applications by Jogad, Seema, Alkhammash, Hend I., Afzal, Neelofer, Loan, Sajad A.

    “…In this work, we design and simulate novel 32 nm carbon nanotube field effect transistor (CNTFET) as well as complementary metal oxide semiconductor…”
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  20. 20

    A Charge Balanced Vertical Power MOSFET with Record High Balliga’s Figure of Merit: Design and Investigation by Nigar, Hafsa, Alkhammash, Hend I., Loan, Sajad A.

    Published in SILICON (01-06-2022)
    “…In this work, we design and simulate a high-performance vertical power MOSFET with a charge balanced drift layer, which modulates the R ON -BV relation from…”
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