Search Results - "Liu, Yongxun"

4.2 K sensitivity-tunable radio frequency reflectometry of a physically defined p-channel silicon quantum dot by Bugu, Sinan, Nishiyama, Shimpei, Kato, Kimihiko, Liu, Yongxun, Murakami, Shigenori, Mori, Takahiro, Ferrus, Thierry, Kodera, Tetsuo

“…We demonstrate the measurement of p-channel silicon-on-insulator quantum dots at liquid helium temperatures by using a radio frequency (rf) reflectometry…”
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RF reflectometry for readout of charge transition in a physically defined p-channel MOS silicon quantum dot by Bugu, Sinan, Nishiyama, Shimpei, Kato, Kimihiko, Liu, Yongxun, Mori, Takahiro, Kodera, Tetsuo

“…We have embedded a physically defined p-channel MOS silicon quantum dot (QD) device into an impedance transformer RC circuit. To decrease the parasitic…”
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Demonstration, analysis, and device design considerations for independent DG MOSFETs by Masahara, M., Yongxun Liu, Sakamoto, K., Endo, K., Matsukawa, T., Ishii, K., Sekigawa, T., Yamauchi, H., Tanoue, H., Kanemaru, S., Koike, H., Suzuki, E.

“…This paper describes a comprehensive study on the threshold voltage (V/sub th/) controllability of four-terminal-driven double-gate (DG) MOSFETs (4T-XMOSFETs)…”
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Fabrication of nano-capillary emitter arrays for ionic liquid electrospray thrusters by Suzuki, Kanta, Nagao, Masayoshi, Liu, Yongxun, Murakami, Katsuhisa, Khumpuang, Sommawan, Hara, Shiro, Takao, Yoshinori

“…In this study, we fabricated nano-capillary emitter arrays for stable ion emission of ionic liquid electrospray thrusters, employing the fabrication of field…”
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High-speed parallel robot dynamic modelling based on PLC by Liu, Yongxun, Zhao, Jingyun, Yao, Yonggang, Cao, Qiuxia, Cui, Jichao

“…This paper first analyses and summarizes the research status of parallel robots and keeps track of the current development status and research prospects of…”
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An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication by Liu, Yongxun, Koga, Kazuhiro, Khumpuang, Sommawan, Nagao, Masayoshi, Matsukawa, Takashi, Hara, Shiro

“…Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been…”
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Fluctuation Analysis of Parasitic Resistance in FinFETs With Scaled Fin Thickness by Matsukawa, T., Endo, K., Ishikawa, Y., Yamauchi, H., O'uchi, S., Yongxun Liu, Tsukada, J., Ishii, K., Sakamoto, K., Suzuki, E., Masahara, M.

“…Measurement-based analysis of the parasitic resistance ( R para ) of FinFETs was extended to investigation of R para fluctuation, which could cause severe…”
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Investigation of piezoresistive effect in p-channel metal-oxide-semiconductor field-effect transistors fabricated on circular silicon-on-insulator diaphragms using cost-effective minimal-fab process by Liu, Yongxun, Tanaka, Hiroyuki, Umeyama, Norio, Koga, Kazuhiro, Khumpuang, Sommawan, Nagao, Masayoshi, Matsukawa, Takashi, Hara, Shiro

“…P-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) with the 〈110〉 or 〈100〉 channel direction have been successfully fabricated on circular…”
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Impact of residual defects caused by extension ion implantation in FinFETs on parasitic resistance and its fluctuation by Matsukawa, Takashi, Liu, Yongxun, Mori, Takahiro, Morita, Yukinori, Otsuka, Shintaro, O'uchi, Shin-ichi, Fuketa, Hiroshi, Migita, Shinji, Masahara, Meishoku

“…•Parasitic resistance and its variability are obstacles for the scaling of FinFETs.•Reducing the fin thickness degrades in parasitic resistance and its…”
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Fabrication of FinFETs by Damage-Free Neutral-Beam Etching Technology by Endo, K., Shuichi Noda, Masahara, M., Kubota, T., Ozaki, T., Samukawa, S., Yongxun Liu, Ishii, K., Ishikawa, Y., Sugimata, E., Matsukawa, T., Takashima, H., Yamauchi, H., Suzuki, E.

“…A high aspect ratio and damage-free vertical ultrathin channel for a vertical-type double-gate MOSFET was fabricated by using low-energy neutral-beam etching…”
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Epitaxial growth of Ge thin film on Si (001) by DC magnetron sputtering by Otsuka, Shintaro, Mori, Takahiro, Morita, Yukinori, Uchida, Noriyuki, Liu, Yongxun, O'uchi, Shin-ichi, Fuketa, Hiroshi, Migita, Shinji, Masahara, Meishoku, Matsukawa, Takashi

“…We have demonstrated that sub-10nm-thick heteroepitaxial Ge films on Si (001) having smooth surfaces can be obtained by DC magnetron sputtering. Ge films grown…”
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Decomposition of On-Current Variability of nMOS FinFETs for Prediction Beyond 20 nm by Matsukawa, T., Liu, Y., O'uchi, S., Endo, K., Tsukada, J., Yamauchi, H., Ishikawa, Y., Ota, H., Migita, S., Morita, Y., Mizubayashi, W., Sakamoto, K., Masahara, M.

“…ON-current (I on ) variability is comprehensively investigated for fin-shaped FETs (FinFETs) by measurement-based analysis. Variation sources of I on are…”
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Suppression of tunneling rate fluctuations in tunnel field-effect transistors by enhancing tunneling probability by Mori, Takahiro, Migita, Shinji, Fukuda, Koichi, Asai, Hidehiro, Morita, Yukinori, Mizubayashi, Wataru, Liu, Yongxun, O uchi, Shin-ichi, Fuketa, Hiroshi, Otsuka, Shintaro, Yasuda, Tetsuji, Masahara, Meishoku, Ota, Hiroyuki, Matsukawa, Takashi

“…This paper discusses the impact of the tunneling probability on the variability of tunnel field-effect transistors (TFETs). Isoelectronic trap (IET)…”
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Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on performance of tunnel field-effect transistors by Morita, Yukinori, Mori, Takahiro, Migita, Shinji, Mizubayashi, Wataru, Fukuda, Koichi, Matsukawa, Takashi, Endo, Kazuhiko, O’uchi, Shin-ichi, Liu, Yongxun, Masahara, Meishoku, Ota, Hiroyuki

“…We evaluate the impact of tunnel junction quality on the performance of tunnel field-effect transistors (TFETs). The interface between epitaxially grown…”
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Variability Origins of Parasitic Resistance in FinFETs With Silicided Source/Drain by Matsukawa, T., Yongxun Liu, Endo, K., Tsukada, J., Ishikawa, Y., Yamauchi, H., O'uchi, S., Sakamoto, K., Masahara, M.

“…Origins of parasitic resistance R para fluctuation were investigated by a measurement-based analysis for fin-shaped FETs (FinFETs) with NiSi in the…”
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Threshold-Voltage Reduction of FinFETs by Ta/Mo Interdiffusion Dual Metal-Gate Technology for Low-Operating-Power Application by Matsukawa, T., Endo, K., Yongxun Liu, O'uchi, S., Ishikawa, Y., Yamauchi, H., Tsukada, J., Ishii, K., Masahara, M., Sakamoto, K., Suzuki, E.

“…In this paper, Ta/Mo interdiffusion dual metal-gate technology, which has an advantage in realizing dual gate work functions without etching of metals from the…”
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Impact of extension implantation conditions of fin field-effect transistors on gate-induced drain leakage by Matsukawa, Takashi, Liu, Yongxun, Mori, Takahiro, Morita, Yukinori, O uchi, Shinichi, Otsuka, Shintaro, Migita, Shinji, Masahara, Meishoku

“…The influence of the extension doping conditions on gate-induced drain leakage (GIDL) has been investigated to optimize fin field-effect transistors (FinFETs)…”
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Bias temperature instability in tunnel field-effect transistors by Mizubayashi, Wataru, Mori, Takahiro, Fukuda, Koichi, Ishikawa, Yuki, Morita, Yukinori, Migita, Shinji, Ota, Hiroyuki, Liu, Yongxun, O uchi, Shinichi, Tsukada, Junichi, Yamauchi, Hiromi, Matsukawa, Takashi, Masahara, Meishoku, Endo, Kazuhiko

“…We systematically investigated the bias temperature instability (BTI) of tunnel field-effect transistors (TFETs). The positive BTI and negative BTI mechanisms…”
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Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication by Yongxun Liu, Kijima, S., Sugimata, E., Masahara, M., Endo, K., Matsukawa, T., Ishii, K., Sakamoto, K., Sekigawa, T., Yamauchi, H., Takanashi, Y., Suzuki, E.

“…The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of…”
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A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel by Yongxun Liu, Masahara, M., Ishii, K., Sekigawa, T., Takashima, H., Yamauchi, H., Suzuki, E.

“…Highly threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness down to 8.5-nm have successfully…”
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