Search Results - "Liu, Tiehui"

Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis by Joshi, Siddhartha, Li, Dawei, Ogrenci-Memik, Seda, Deptuch, Grzegorz, Hoff, James, Jindariani, Sergo, Liu, Tiehui, Olsen, Jamieson, Tran, Nhan

“…In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use…”
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A content addressable memory with multi-Vdd scheme for low power tunable operation by Joshi, Siddhartha, Dawei Li, Ogrenci-Memik, Seda, Deptuch, Grzegorz, Hoff, James, Jindariani, Sergo, Tiehui Liu, Olsen, Jamieson, Nhan Tran

“…This paper reports on a content addressable memory (CAM) employing a multi-Vdd scheme for low power pattern recognition applications. The complete design,…”
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A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade by Zhang, Wei, Sun, Hanhan, Edwards, Christopher, Gong, Datao, Huang, Xing, Liu, Chonghan, Liu, Tiankuan, Liu, Tiehui, Olsen, Jamieson, Sun, Quan, Sun, Xiangming, Wu, Jinyuan, Ye, Jingbo, Zhang, Li

“…We present the design and test results of a time-to-digital-converter (TDC). The TDC will be a part of the readout Application-Specific Integrated Circuit…”
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A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoMS in 65-nm CMOS by Fang, Liang, Wen, Xianshan, Fu, Tao, Wang, Guanhua, Miryala, Sandeep, Liu, Tiehui Ted, Gui, Ping

“…This article presents a 2.56-GS/s 12-bit eight-channel interleaved analog-to-digital converter (ADC) that achieves an FOM<inline-formula> <tex-math…”
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A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoM S in 65-nm CMOS by Fang, Liang, Wen, Xianshan, Fu, Tao, Wang, Guanhua, Miryala, Sandeep, Liu, Tiehui Ted, Gui, Ping

“…This article presents a 2.56-GS/s 12-bit eight-channel interleaved analog-to-digital converter (ADC) that achieves an FOM[Formula Omitted] of 156.6 dB at near…”
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Performance Study of the First 2-D Prototype of Vertically Integrated Pattern Recognition Associative Memory by Deptuch, Gregory, Hoff, James, Jindariani, Sergo, Joshi, Siddhartha, Li, Dawei, Liu, Tiehui, Ogrenci-Memik, Seda, Olsen, Jamieson, Tran, Nhan

“…Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second…”
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A methodology for power characterization of associative memories by Dawei Li, Joshi, Siddhartha, Ogrenci-Memik, Seda, Hoff, James, Jindariani, Sergo, Tiehui Liu, Olsen, Jamieson, Tran, Nhan

“…Content Addressable Memories (CAM) have become increasingly more important in applications requiring high speed memory search due to their inherent massively…”
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Machine Learning Based Anomaly Clustering Study for Bolt Tightening System by Liu, Tiehui, Hu, Shan, Bing, Zhigang, Zhao, Di

“…In the context of Industry 4.0, the tightening quality of bolts is still critical to product performance and safety. In order to improve the abnormal data…”
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Prototype performance studies of a full mesh ATCA-based general purpose data processing board by Okumura, Yasuyuki, Olsen, Jamieson, Liu, Tiehui Ted, Hang Yin

“…High luminosity conditions at the LHC pose many unique challenges for potential silicon based track trigger systems. One of the major challenges is data…”
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Status of the Baar experiment by Liu, Tiehui (Ted)

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Status of the B a[formula omitted]ar experiment by Liu, Tiehui (Ted)

“…This is a status report from the B a B ar experiment at the Stanford Linear Accelerator Center. It has been designed to measure time-dependent asymmetries in…”
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ETROC1: The First Full Chain Precision Timing Prototype ASIC for CMS MTD Endcap Timing Layer Upgrade by Huang, Xing, Sun, Quan, Gong, Datao, Gwak, Piljun, Kim, Doyeong, Lee, Jongho, Liu, Chonghan, Liu, Tiankuan, Liu, Tiehui, Los, Sergey, Miryala, Sandeep, Nanda, Shirsendu, Olsen, Jamieson, Sun, Hanhan, Wu, Jinyuan, Ye, Jingbo, Ye, Zhenyu, Zhang, Li, Zhang, Wei

“…We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD…”
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Workload Dependent Design and Power Modeling of Pattern Recognition Associative Memories by Joshi, Siddhartha, Ogrenci-Memik, Seda, Hoff, James, Liu, Tiehui

“…In this work, we analyze and model the most significant parameters for the power consumption of a content addressable memory (CAM) based Pattern Recognition…”
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Review of bottomonium measurements from CMS by Hu, Zhen, Leonardo, Nuno T, Liu, Tiehui Ted, Haytmyradov, Maksat

“…International Journal of Modern Physics A, Vol. 32, Nos. 19n20 (2017) 1730015 We review the results on the bottomonium system from the CMS experiment at the…”
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A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade by Zhang, Wei, Sun, Hanhan, Edwards, Christopher, Gong, Datao, Huang, Xing, Liu, Chonghan, Liu, Tiankuan, Liu, Tiehui, Olsen, Jamieson, Sun, Quan, Sun, Xiangming, Wu, Jinyuan, Ye, Jingbo, Zhang, Li

“…We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain…”
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Charged Particle Tracking in Real-Time Using a Full-Mesh Data Delivery Architecture and Associative Memory Techniques by Ajuha, Sudha, Shinoda, Ailton Akira, Ramalho, Lucas Arruda, Baulieu, Guillaume, Boudoul, Gaelle, Casarsa, Massimo, Cascadan, Andre, Clement, Emyr, de Paiva, Thiago Costa, Das, Souvik, Dutta, Suchandra, Eusebi, Ricardo, Fedi, Giacomo, Ferreira, Vitor Finotti, Hahn, Kristian, Hu, Zhen, Jindariani, Sergo, Konigsberg, Jacobo, Liu, Tiehui, Low, Jia Fu, MacDonald, Emily, Olsen, Jamieson, Palla, Fabrizio, Pozzobon, Nicola, Rathjens, Denis, Ristori, Luciano, Rossin, Roberto, Sung, Kevin, Tran, Nhan, Trovato, Marco, Ulmer, Keith, Vaz, Mario, Viret, Sebastien, Wu, Jin-Yuan, Xu, Zijun, Zorzetti, Silvia

“…We present a flexible and scalable approach to address the challenges of charged particle track reconstruction in real-time event filters (Level-1 triggers) in…”
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The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL by Sun, Quan, Dogra, Sunil M, Edwards, Christopher, Gong, Datao, Gray, Lindsey, Huang, Xing, Joshi, Siddhartha, Lee, Jongho, Liu, Chonghan, Liu, Tiehui, Liu, Tiankuan, Los, Sergey, Moon, Chang-Seong, Oh, Geonhee, Olsen, Jamieson, Ristori, Luciano, Sun, Hanhan, Wang, Xiao, Wu, Jinyuan, Ye, Jingbo, Ye, Zhenyu, Zhang, Li, Zhang, Wei

“…The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in…”
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Performance Study of the First 2D Prototype of Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) by Deptuch, Gregory, Hoff, James, Jindariani, Sergo, Liu, Tiehui, Olsen, Jamieson, Tran, Nhan, Joshi, Siddhartha, Li, Dawei, Ogrenci-Memik, Seda

“…Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second…”
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Prototype performance studies of a Full Mesh ATCA-based General Purpose Data Processing Board by Okumura, Yasuyuki, Olsen, Jamieson, Liu, Tiehui Ted, Yin, Hang

“…High luminosity conditions at the LHC pose many unique challenges for potential silicon based track trigger systems. One of the major challenges is data…”
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Development of an Intelligent Platform Management controller for the Pulsar IIb by Ramalho, Lucas A., Paiva, Thiago C., Iope, Rogerio L., Leal, Beraldo C., Liu, Tiehui T., Olsen, Jamieson, Shinoda, Ailton A., Vaz, Mario

“…The Pulsar IIb is a general purpose FPGA-based processor board designed for full mesh ATCA backplanes. This hardware was originally designed to support Level-1…”
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