Search Results - "Liu, Changze"
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1
In vitro inhibitory effect of zingerone on TNFα-stimulated fibroblast-like synoviocytes
Published in In vitro cellular & developmental biology. Animal (01-09-2023)“…Targeting Fibroblast-like synoviocytes (FLSs) is an attractive complementary approach for RA therapy. This study aimed to investigate the inhibitory effects of…”
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2
Experimental study on the oxide trap coupling effect in metal oxide semiconductor field effect transistors with HfO2 gate dielectrics
Published in Applied physics letters (30-06-2014)“…In this Letter, the coupling effect between multi-traps in HfO2 gate dielectrics is experimentally studied in scaled high-κ/metal-gate metal oxide…”
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3
Hot carrier reliability characterization in consideration of self-heating in FinFET technology
Published in 2016 IEEE International Reliability Physics Symposium (IRPS) (01-04-2016)“…A severity of hot carrier injection (HCI) in PFET becomes worse than NFET at elevated temperatures. This new observation is further found to be due to the…”
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4
Investigation of HCI effects in FinFET based ring oscillator circuits and IP blocks
Published in 2017 IEEE International Reliability Physics Symposium (IRPS) (01-04-2017)“…Hot carrier injection (HCI) effect with circuits running at very high frequency through overdrive (OD) can manifest under very long stress time and lower…”
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5
Systematical study of 14nm FinFET reliability: From device level stress to product HTOL
Published in 2015 IEEE International Reliability Physics Symposium (01-04-2015)“…In this paper, fundamental reliability findings in 14nm bulk FinFET technology, are systematically investigated. From device and Ring Oscillator stress to…”
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6
Negative-Bias Temperature Instability in Gate-All-Around Silicon Nanowire MOSFETs: Characteristic Modeling and the Impact on Circuit Aging
Published in IEEE transactions on electron devices (01-12-2010)“…In this paper, the negative-bias temperature instability (NBTI) in p-type gate-all-around silicon nanowire MOSFETs (SNWTs) is investigated for circuit aging…”
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New insights into 10nm FinFET BTI and its variation considering the local layout effects
Published in 2017 IEEE International Reliability Physics Symposium (IRPS) (01-04-2017)“…In this paper, BTI variation of 10nm FinFET is experimentally studied taking into account of the local layout effects. Although Fin shape is further optimized…”
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8
New observations on the random telegraph noise induced Vth variation in nano-scale MOSFETs
Published in 2014 IEEE International Reliability Physics Symposium (01-06-2014)“…In this paper, random telegraph noise (RTN) induced ΔV th variation under the worst bias condition is experimentally investigated. The results show that ΔV th…”
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9
HCI and NBTI induced degradation in gate-all-around silicon nanowire transistors
Published in Microelectronics and reliability (01-09-2011)“…The silicon nanowire transistor (SNWT) with gate-all-around (GAA) structure can be considered as one of the potential candidates for ultimate scaling due to…”
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10
Observation of strong reflection of electron waves exiting a ballistic channel at low energy
Published in AIP advances (01-06-2016)“…Wave scattering by a potential step is a ubiquitous concept. Thus, it is surprising that theoretical treatments of ballistic transport in nanoscale devices,…”
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Deep understanding of AC RTN in MuGFETs through new characterization method and impacts on logic circuits
Published in 2013 Symposium on VLSI Technology (01-06-2013)“…The AC random telegraph noise (AC RTN) in scaled multi-gate FETs (MuGFETs) is experimentally studied for the first time, which is found to have enhanced AC…”
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12
Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01-09-2011)“…The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the…”
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Conference Proceeding -
13
Characteristics of Gate Current Random Telegraph Signal Noise in SiON/HfO2/TaN p-Type Metal--Oxide--Semiconductor Field-Effect Transistors under Negative Bias Temperature Instability Stress Condition
Published in Jpn J Appl Phys (01-04-2010)“…Gate dielectric traps are becoming a major concern in the high-$k$/metal gate devices. In this paper, new experimental results and in-depth study on gate…”
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14
New observations on the AC random telegraph noise (AC RTN) in nano-MOSFETs
Published in Proceedings of Technical Program of 2012 VLSI Technology, System and Application (01-04-2012)“…The random telegraph noise (RTN) is becoming a critical issue for variability and reliability in nanoscale MOSFETs. Since devices actually operate under AC…”
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Conference Proceeding -
15
New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability
Published in 2017 IEEE International Electron Devices Meeting (IEDM) (01-12-2017)“…In this paper, hot carrier degradation (HCD) in FinFET is studied for the first time from trap-based approach rather than conventional carrier-based approach,…”
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16
Inflection Points in GAA NS-FET to C-FET Scaling Considering Impact of DTCO Boosters
Published in IEEE transactions on electron devices (01-04-2024)“…Complimentary FETs (C-FETs) enable aggressive standard cell height reduction, facilitating on-target area scaling without shrinking contacted gate pitch (CGP)…”
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Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-07-2022)“…With continued scaling, the transistor aging induced by hot carrier injection (HCI) and bias temperature instability (BTI) causes an increasing failure of…”
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Optimization and Benchmarking FinFETs and GAA Nanosheet Architectures at 3-nm Technology Node: Impact of Unique Boosters
Published in IEEE transactions on electron devices (01-08-2022)“…Using a full design-technology cooptimization (DTCO) framework, we benchmark gate-all-around (GAA) nanosheet (NS) FETs against FinFETs at 3-nm logic technology…”
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New insights into oxide traps characterization in gate-all-around nanowire transistors with TiN metal gates based on combined Ig-Id RTS technique
Published in 2009 Symposium on VLSI Technology (01-06-2009)“…By using combined gate current and drain current random telegraph signal noise (I g -I d RTS) technique, both electron and hole traps within the gate stack of…”
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20
Peimine suppresses collagen-induced arthritis, activated fibroblast-like synoviocytes and TNFα-induced MAPK pathways
Published in International immunopharmacology (01-10-2022)“…[Display omitted] •Peimine suppressed synovitis and bone destruction in CIA rats.•Peimine inhibited TNFα-induced destructive behaviors of arthritic…”
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