Search Results - "Litta, E. D."

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery by Bastos, J. P., O'Sullivan, B. J., Franco, J., Tyaginov, S., Truijen, B., Chasin, A., Degraeve, R., Kaczer, B., Ritzenthaler, R., Capogreco, E., Litta, E. D., Spessot, A., Higashi, Y., Yoon, Y., Machkaoutsan, V., Fazan, P., Horiguchi, N.

“…This paper reports BTI trends in high-voltage transistors for memory periphery devices with SiO2/Poly-Si and High-K/Metal gate stacks. For PBTI, we present an…”
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Impact of Fin Height on Bias Temperature Instability of Memory Periphery FinFETs by Boubaaya, M., Benaceur-Doumaz, D., Ferhat Hamida, A., Djezzar, B., Spessot, A., Linten, D., Horiguchi, N., O'Sullivan, B. J., Franco, J., Litta, E. D., Ritzenthaler, R., Dupuy, E., Machkaoutsan, V., Fazan, P., Kim, C.

“…Fin height dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high-κ metal gate (HKMG) FinFETs transistors is…”
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Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration by Mertens, H., Ritzenthaler, R., Pena, V., Santoro, G., Kenis, K., Schulze, A., Litta, E. D., Chew, S. A., Devriendt, K., Chiarella, R., Demuynck, S., Yakimets, D., Jang, D., Spessot, A., Eneman, G., Dangol, A., Lagrain, P., Bender, H., Sun, S., Korolik, M., Kioussis, D., Kim, M., Bu, Chen, S. C., Cogorno, M., Devrajan, J., Machillot, J., Yoshida, N., Kim, N., Barla, K., Mocuta, D., Horiguchi, N.

“…We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs with in-situ doped source-drain stressors and dual work function…”
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Impact of Dimensions of Memory Periphery FinFETs on Bias Temperature Instability by Boubaaya, Mohamed, O'Sullivan, B. J., Djezzar, Boualem, Franco, J., Litta, E. D., Ritzenthaler, R., Dupuy, E., Machkaoutsan, Vladimir, Fazan, Pierre, Kim, C., Bennaceur-Doumaz, D., Hamida, A. Ferhat, Spessot, A., Linten, D., Horiguchi, N.

“…Fin height and width dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high-<inline-formula> <tex-math…”
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Reliability of Barrierless PVD Mo by Tierno, Davide, Hosseini, M., van der Veen, M., Dangol, A., Croes, K., Demuynck, S., Tokei, Zs, Litta, E.D., Horiguchi, N.

“…We evaluate the reliability of barrierless Mo metallization on various dielectrics that are used in both BEOL and MOL integration schemes. In particular, we…”
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Interface engineering of Ge using thulium oxide: Band line-up study by Mitrovic, I.Z., Althobaiti, M., Weerakkody, A.D., Sedghi, N., Hall, S., Dhanak, V.R., Chalker, P.R., Henkel, C., Dentoni Litta, E., Hellström, P.-E., Östling, M.

“…•Thulium oxide layers on germanium were investigated.•The valence band offset was found to be 2.95eV.•The band gap of thulium oxide was found to be 5.3eV from…”
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Low-frequency noise in high-k LaLuO3/TiN MOSFETs by Olyaei, M., Malm, B. G., Litta, E. D., Hellstrom, P-E, Ostling, M.

“…The implementation of high-k gate stacks has enabled further scaling in CMOS technology. However it is still challenging due to increased number of trap…”
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A study of low-frequency noise on high-k/metal gate stacks with in situ SiOx interfacial layer by Olyaei, M., Malm, B. G., Litta, E. D., Hellstrom, P. E., Ostling, M.

“…Low-frequency noise of HfO 2 /TiN nMOSFETs with different SiO x interfacial layer (IL) thicknesses is presented. It is observed that chemically formed thin ILs…”
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