Search Results - "Ling, Ho Siow"

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  1. 1

    Heating rate dependent delamination of metal–polymer interfaces: experiments and modeling by Ho, Siow Ling, Joshi, Shailendra P., Tay, Andrew A. O.

    Published in International journal of fracture (01-06-2014)
    “…Bimaterial interfaces in microelectronics packages are the most common regions of failure under thermo-mechanical excursions. In this work, we report…”
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    Journal Article
  2. 2

    Comprehensive Study on the Interactions of Multiple Die Shift Mechanisms During Wafer Level Molding of Multichip-Embedded Wafer Level Packages by Ho Siow Ling, Bu Lin, Chong Ser Choong, Velez, Sorono Dexter, Chai Tai Chong, Xiaowu Zhang

    “…Comprehensive numerical and experimental analyses were performed to investigate the issue of die shift during the 12-in wafer level molding process of…”
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    Journal Article
  3. 3

    3-D Modeling and Characterization for Die Attach Process by Bu, Lin, Ching, Wai Leong, Ling, Ho Siow, Rhee, Min Woo, Fen, Yong Puay

    “…A new 3-D model for the die attach (DA) process is established and validated in this paper. With this model, the fluid flow characteristics of the DA process…”
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    Journal Article
  4. 4

    Experiments and Three-Dimensional Modeling of Delamination in an Encapsulated Microelectronic Package Under Thermal Loading by Siow Ling Ho, Joshi, Shailendra P., Tay, Andrew A. O.

    “…Interfacial delamination in encapsulated silicon devices has been a great reliability concern in IC packaging. Experimental testing of a transparent quad flat…”
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    Journal Article
  5. 5

    High power SiC inverter module packaging solutions for junction temperature over 220°C by Woo, Daniel Rhee Min, Hwang How Yuan, Li, Jerry Aw Jie, Ho Siow Ling, Lee Jong Bum, Zhang Songbai, Zhang Hengyun, Selvaraj, Susai Lawrence, Velez, Sorono Dexter, Singh, Ravinder Pal

    “…The SiC based high power 3 phase inverter module with double side cooling structure was developed. By applying flipchip bonding of SiC based high power DMOSFET…”
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    Conference Proceeding
  6. 6

    Optimization of the wafer level molding process for high power device module by Lin Bu, Siow Ling Ho, Velez Sorono, Dexter, Woo, Daniel Rhee Min

    “…High power modules are indispensible in our future automotive, aerospace and green & renewable energy industry. However, a lot of issues rise along with the…”
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    Conference Proceeding
  7. 7

    3D vs 2D modeling of the effect of die size on delamination in encapsulated IC packages by Siow Ling Ho, Tay, Andrew A. O.

    “…In a previous 2D parametric study, it was found that the die size appear to have no significant effect on the likelihood of delamination at the pad-encapsulant…”
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    Conference Proceeding
  8. 8

    Thermal-mechanical considerations of a novel power module with high junction temperature by Ho Siow Ling, Lee Yong Jiun, Hwang How Yuan, Zhang Heng Yun, Rhee, Daniel

    “…Mechanical and thermal analyses are performed for a power module with target junction temperature of 220°C. The initial design of the package consists of six…”
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    Conference Proceeding
  9. 9

    Moisture diffusion modeling and its impact on fracture mechanics parameters with regard to a PQFP by Siow Ling Ho, Tay, Andrew A O

    “…Absorption of moisture by plastic packages increases the susceptibility of packages to interfacial delamination. Accurate determination of moisture…”
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    Conference Proceeding
  10. 10

    Impact of advanced materials on power cycling performance and process dependent stresses of QFN by Ho Siow Ling, Ching, E. W. L., Yi, G. H. Y., Rhee, Min Woo Daniel

    “…Due to different demands, there are many types of die attach technologies in the market. In this work, die attach materials such as solder, silver filled…”
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    Conference Proceeding
  11. 11

    A numerical analysis of penny-shaped delaminations in an encapsulated silicon module by Siow Ling Ho, Tay, A. A. O.

    “…Modeling penny-shaped delaminations in encapsulated silicon devices and modules such as solar photovoltaic modules, multichip modules or plastic quad flat…”
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    Conference Proceeding
  12. 12

    Cohesive zone modeling of 3D delamination in encapsulated silicon devices by Siow Ling Ho, Joshi, S. P., Tay, A. A. O.

    “…Interfacial delamination in encapsulated silicon devices has been a great reliability concern in IC packaging. Experimental testing of a transparent Quad Flat…”
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    Conference Proceeding
  13. 13

    A numerical study of 3D interfacial delamination in PQFP packages by Siow Ling Ho, Tay, A.A.O.

    “…Interfacial delamination of the leadframe pad and encapsulant is the precursor to type I popcorn cracking. Due to high stress concentration at the corner of…”
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    Conference Proceeding
  14. 14

    Interaction of multiple delaminations and die in a plastic IC package by Siow Ling Ho, Jiyin Yu, Tay, A A O

    “…To lend more confidence to the engineers adopting the fracture mechanics approach in the study of delamination in IC packages, a series of studies is performed…”
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    Conference Proceeding
  15. 15

    Effect of shapes of crack fronts on the mechanics of 3D interfacial delamination in IC packages by Siow Ling Ho, Tay, A.A.O.

    “…Interfacial delamination of the leadframe pad and encapsulant is the precursor to type I popcorn cracking. Due to high stress concentration at the corner of…”
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    Conference Proceeding
  16. 16

    Effect of the die edge and multiple delaminations on the mechanics of delamination in a PQFP by Siow Ling Ho, Jiyin Yu, Tay, Andrew A O

    “…Interfacial delamination between the lead frame pad and the encapsulant can be a concern as the delamination at this interface is the precursor to Type I…”
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    Conference Proceeding
  17. 17

    Interaction of multiple delaminations in a PQFP by Siow Ling Ho, Jiyin Yu, Tay, A A O

    “…To lend more confidence to the engineers adopting the fracture mechanics approach in the study of delamination in IC packages, a series of studies is performed…”
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    Conference Proceeding
  18. 18

    Optimization of Reliability of Copper Column Flip Chip Packages with Variable Compliance Interconnects by Tay, A.A.O., Siow Ling Ho

    “…This paper describes a parametric study of the reliability of solder joints in wafer level flip chip packages that employ copper column interconnects. In this…”
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    Conference Proceeding