Reliability improvements for advanced Wafer Level packaging

Over ten years ago, Wafer Level Chip Scale Packaging (WLCSP) began with very small packages having solderball counts of 2-6 I/O. Over the years, the I/O count has grown, but the industry perception has always been that WLCSPs are limited to low I/O count applications. Within the last year, there has...

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Bibliographic Details
Published in:	3rd Electronics System Integration Technology Conference ESTC pp. 1 - 6
Main Authors:	Hunt, John, Huang, Danial, Chiu, Jessica, Liu, Maggie M C, Lin, Junior, Lou, J W, Chienfan Chen, Chin-Li Kao
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-09-2010
Subjects:	Artificial intelligence Copper Manganese Nickel Performance evaluation Polymers
Online Access:	Get full text
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Summary:	Over ten years ago, Wafer Level Chip Scale Packaging (WLCSP) began with very small packages having solderball counts of 2-6 I/O. Over the years, the I/O count has grown, but the industry perception has always been that WLCSPs are limited to low I/O count applications. Within the last year, there has been a growing demand for WLCSP packages with I/O counts greater than 150, with some applications requiring I/O's of more than 300. As each generation of WLCSP has grown in complexity, it has strained the capabilities of the processes, material sets, and structures that performed satisfactorily in previous generations. It has been observed that while manufacturing WLCSP products for a wide variety of customers, as we go above 100 I/O, and then again above 150 I/O, the structural and compositional parameters of the WLCSP have had to be modified in order to pass the end customer's reliability requirements. This paper will explore the impact of material, process, and structural variations to a large scale WLCSP, on Board Level Reliability.
ISBN:	9781424485536 1424485533
DOI:	10.1109/ESTC.2010.5642883