Search Results - "Lime, Francois"
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Unified Charge Control Model for Back-Gated 2-D Field Effect Transistors
Published in IEEE transactions on electron devices (01-01-2024)“…A physics-based analytical dc compact model for single back-gated MoS2 field effect transistors (FETs) is presented. The model is developed by calculating the…”
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Compact I-V model for back-gated and double-gated TMD FETs
Published in Solid-state electronics (01-09-2023)“…•A physics-based analytical DC compact model for double and single gate TMD FETs is presented.•The charge density inside the 2D layer is expressed in terms of…”
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Journal Article -
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A Complete Charge-Based Capacitance Model for IGZO TFTs
Published in IEEE electron device letters (01-05-2019)“…We present a new complete capacitance model for the amorphous indium-gallium-zinc-oxide (IGZO) thin-film-transistor (TFT), valid in the above-threshold and…”
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A simple compact model for long-channel junctionless Double Gate MOSFETs
Published in Solid-state electronics (01-02-2013)“…► We developed an analytical compact model for the drain current of long channel junctionless Double Gate MOSFETs. ► The model is much simpler and covers…”
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Analytical modeling of capacitances in tunnel-FETs including the effect of Schottky barrier contacts
Published in Solid-state electronics (01-09-2019)“…In this paper, a charge-based analytical model for intrinsic capacitances in tunnel field-effect transistors (TFETs) is presented. The model is derived for a…”
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A compact explicit DC model for short channel Gate-All-Around junctionless MOSFETs
Published in Solid-state electronics (01-05-2017)“…•A DC compact model for the cylindrical GAA MOSFET is proposed.•Short channel effects are taken into accounted.•The model is explicit with relatively simple…”
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A quantum wave based compact modeling approach for the current in ultra-short DG MOSFETs suitable for rapid multi-scale simulations
Published in Solid-state electronics (01-11-2017)“…•The presented model is based on an non-iterative NEGF formalism.•Channel length from 6nm to 30nm of DG MOSFETs are considered.•Source-to-drain tunneling and…”
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Journal Article -
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A Quasi-Two-Dimensional Compact Drain-Current Model for Undoped Symmetric Double-Gate MOSFETs Including Short-Channel Effects
Published in IEEE transactions on electron devices (01-06-2008)“…A drain-current model for undoped symmetric double-gate MOSFETs is proposed. Channel-length modulation and drain-induced barrier lowering are modeled by using…”
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3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors
Published in Solid-state electronics (01-11-2011)“…In this work, a model is developed in order to obtain analytical expressions of the subthreshold characteristics of advanced Pi-gate FET transistors. Based on…”
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Journal Article Conference Proceeding -
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Gate leakage current partitioning in nanoscale double gate MOSFETs, using compact analytical model
Published in Solid-state electronics (01-09-2012)“…► We presented a model of the gate current partitioning into the source and drain for a DG MOSFETs structure. ► Model based on a compact analytical gate…”
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A complete and Verilog-A compatible Gate-All-Around long-channel junctionless MOSFET model implemented in CMOS inverters
Published in Microelectronics (01-11-2015)“…In this paper, we present the results of the implementation of a complete DC and AC Gate-All-Around (GAA) long-channel junctionless MOSFET model in Verilog-A…”
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Cryogenic Temperature and Doping Analysis of Source-to-Drain Tunneling Current in Ultrashort-Channel Nanosheet MOSFETs
Published in IEEE transactions on electron devices (01-03-2022)“…This work analyzes the impact of doping concentration on the temperature-dependent subthreshold current and swing saturation due to direct source-to-drain…”
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Quasi-Compact Model of Direct Source-to-Drain Tunneling Current in Ultrashort-Channel Nanosheet MOSFETs by Wavelet Transform
Published in IEEE transactions on electron devices (01-01-2022)“…We present an analytical approach for the calculation of direct source-to-drain tunneling (DSDT) probability of electrons in gate-all-around (GAA) silicon…”
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A Compact Explicit Model for Long-Channel Gate-All-Around Junctionless MOSFETs. Part I: DC Characteristics
Published in IEEE transactions on electron devices (01-09-2014)“…In this paper, we solved Poisson equation in cylindrical coordinates using approximations to obtain a compact model for the drain current of long-channel…”
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Journal Article -
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Compact DC and Quasi-Static Capacitances Modeling of a-Si:H TFTs, Including Parasitic Capacitances
Published in IEEE transactions on electron devices (01-07-2021)“…This article presents a compact model for the drain current and capacitances of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs). The model…”
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Journal Article -
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Electrical studies of semiconductor–dielectric interfaces
Published in Journal of materials science. Materials in electronics (01-09-2006)“…Issue Title: Oxides in Electronics, Dedicated to Cyril Hogarth In this paper, a review of the physical properties and characterization techniques of…”
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Journal Article -
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Impact of On-Current on the Static and Dynamic Performance of TFET Inverters
Published in 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (14-10-2019)“…Concerning the innovations in architecture of tunnel-field effect transistor (TFET), the potential to achieve higher on-current increases. In respect thereof,…”
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Conference Proceeding -
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A Compact Explicit Model for Long-Channel Gate-All-Around Junctionless MOSFETs. Part II: Total Charges and Intrinsic Capacitance Characteristics
Published in IEEE transactions on electron devices (01-09-2014)“…Analytical and explicit expressions are derived for intrinsic capacitances of the junctionless gate-all-around transistor, from the charge-control model, valid…”
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Journal Article -
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Equivalent DG Dimensions Concept for Compact Modeling of Short-Channel and Thin Body GAA MOSFETs Including Quantum Confinement
Published in IEEE transactions on electron devices (01-12-2020)“…In this work, short-channel effects (SCEs) in cylindrical gate-all-around (GAA) MOSFETs with intrinsic or lightly doped channels are analytically described by…”
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