Search Results - "Libous, J."

Power distribution networks for system-on-package: status and challenges by Swaminathan, M., Kim, Joungho, Novak, I., Libous, J.P.

“…The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product…”
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The Use of Accelerated Full-Wave Modeling to Analyze Power Island Coupling in a HyperBGA SCM by Morsey, J., Deutsch, A., Libous, J.P., Surovic, C., Rubin, B.J., Lijun Jiang, Eisenberg, L.

“…Presented here are results and recommendations for reducing coupling between adjacent power islands based on full-wave simulations of a HyperBGA SCM…”
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Macro-modeling of non-linear I/O drivers using spline functions and finite time difference approximation by Mutnury, B., Swaminathan, M., Libous, J.

“…In this paper a modeling methodology using spline functions with finite time difference is proposed for modeling digital I/O drivers. Digital driver circuits…”
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Macromodeling of nonlinear digital I/O drivers by Mutnury, B., Swaminathan, M., Libous, J.P.

“…In this paper, a modeling technique using spline functions with finite time difference approximation is discussed for modeling moderately nonlinear digital…”
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Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA by Libous, J.P., O'Connor, D.P.

“…This paper presents the simultaneous switching noise (SSN) measurements, modeling, and simulation of a flip-chip complementary metal-oxide-semiconductor (CMOS)…”
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Modeling of power supply noise using efficient macro-model of non-linear driver by Mutnury, B., Swaminathan, M., Libous, J.

“…In this paper, power supply noise is modeled accurately using efficient macro-models of nonlinear digital drivers. A spline function with finite time…”
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Modeling and simulation of core switching noise on a package and board by Na, N., Swaminathan, M., Libous, J., O'Connor, D.

“…This paper presents simulation and analysis of core switching noise on a CMOS test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA)…”
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Effect of substrate resistivity on switching noise in on-chip power distribution networks by Jifeng Mao, Swaminathan, M., Libous, J., O'Connor, D.

“…This paper describes the effect of substrate loss on simultaneous switching noise (SSN) in on-chip power distribution networks (PDN). Conformal mapping and…”
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Electromagnetic modelling of switching noise in on-chip power distribution networks by Jifeng Mao, Woopoung Kim, Suna Choi, Swaminathan, M., Libous, J., O'connor, D.

“…An investigation of the effect of substrate loss on simultaneous switching noise (SSN) in on-chip power distribution networks is presented. In order to…”
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Modeling and simulation of core switching noise for ASICs by Nanju Na, Jinwoo Choi, Swaminathan, M., Libous, J.R., O'Connor, D.P.

“…This paper presents simulation and analysis of core switching noise for a CMOS ASIC test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA)…”
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The use of accelerated full-wave modeling to analyze power island coupling in a HyperBGA SCM by Morsey, J., Deutsch, A., Libous, J.P., Surovic, C., Rubin, B.J., Jiang, L., Eisenberg, L.

“…Presented here are results and recommendations for reducing coupling between adjacent power islands based on full-wave simulations of a HyperBGA SCM…”
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Comparison of multilayer organic and ceramic package simultaneous switching noise measurements using a 0.16 /spl mu/m CMOS test chip by Budell, T., Audet, J., Kent, D., Libous, J., O'Connor, D., Rosser, S., Tremble, E.

“…This paper presents a comparison of simultaneous switching-output noise measurements taken with a 0.16 /spl mu/m CMOS test chip on two flip-chip multilayer…”
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A one-million-circuit CMOS ASIC logic family by Gregor, R., Ng, C., Libous, J., Carter, E., Beaudoin, R., Chu, A., Grindel, D., Kinney, J., Lee, M., Mentes, L., Oppold, J., Russell, M., Secor, A., Yenik, G.

“…Metallization and device channel length enhancements to an existing 0.5-/spl mu/m CMOS process are exploited in the design of a high-density ASIC…”
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Characterization of flip-chip CMOS ASIC simultaneous switching noise on multilayer organic and ceramic BGA/CGA packages by Libous, J.P.

“…This paper presents the characterization of flip-chip CMOS ASIC core logic and I/O simultaneous switching noise on several types of high density multilayer…”
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Effect of organic package core via pitch reduction on power distribution performance by Audet, J., O'Connor, D.P., Grinberg, M., Libous, J.P.

“…Advances in CMOS technology continue to provide increased circuit density and performance at a lower cost. Die size and cost can be further reduced for I/O…”
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I/O cell placement and electrical checking methodology for ASICs with peripheral I/Os by Yasar, G., Chiu, C., Proctor, R.A., Libous, J.P.

“…Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper…”
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