Search Results - "Liao, A.S.H."

VB-1 an N-channel In 0.53 Ga 0.47 As plasma oxide insulated gate inversion-mode fet by Liao, A.S.H., Tell, B., Leheny, R.F., Chang, T.Y., Nahory, R.E.

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VB-1 an N-channel In0.53Ga0.47As plasma oxide insulated gate inversion-mode fet by Liao, A.S.H., Tell, B., Leheny, R.F., Chang, T.Y., Nahory, R.E.

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An In 0.53 Ga 0.47 As/Si 3 N 4 n-channel inversion mode MISFET by Liao, A.S.H., Leheny, R.F., Nahory, R.E., De Winter, J.C.

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An In0.53Ga0.47As/Si3N4n-channel inversion mode MISFET by Liao, A.S.H., Leheny, R.F., Nahory, R.E., De Winter, J.C.

“…We describe the operation of an n-channel inversion-mode In 0.53 Ga 0.47 As MISFET with a Si 3 N 4 insulating layer. This device exhibits a transconductance of…”
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Silicon Oxide enhanced Schottky gate In 0.53 Ga 0.47 As FET's with a self-aligned recessed gate structure by Cheng, C.L., Liao, A.S.H., Chang, T.Y., Caridi, E.A., Coldren, L.A., Lalevic, B.

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An In 0.53 Ga 0.47 As p-channel MOSFET with plasma-grown native oxide insulated gate by Liao, A.S.H., Tell, B., Leheny, R.F., Nahory, R.E., DeWinter, J.C., Martin, R.J.

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Monolithic integration of a planar embedded InGaAs p-i-n detector with InP depletion-mode FET's by Tell, B., Liao, A.S.H., Brown-Goebeler, K.F., Bridges, T.J., Burkhardt, G., Chang, T.Y., Bergano, N.S.

“…We report the operation of a fully integrated p-i-n FET circuit based on a planar embedded In 0.53 Ga 0.47 As p-i-n detector and load resistor with InP…”
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Silicon Oxide enhanced Schottky gate In0.53Ga0.47As FET's with a self-aligned recessed gate structure by Cheng, C.L., Liao, A.S.H., Chang, T.Y., Caridi, E.A., Coldren, L.A., Lalevic, B.

“…We present the fabrication and characterization of an In 0.53 Ga 0.47 As enhanced Schottky gate FET with a self-aligned recessed gate structure. A thin layer…”
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VIA-5 enhanced Schottky-gate InGaAs field-effect transistors using e-beam evaporated silicon oxide by Cheng, C.L., Lalevic, B., Liao, A.S.H., Chang, T.Y., Caridi, E.A., Coldren, L.A.

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Submicrometer self-aligned recessed gate InGaAs MISFET exhibiting very high transconductance by Cheng, C.L., Liao, A.S.H., Chang, T.Y., Leheny, R.F., Coldren, L.A., Lalevic, B.

“…A new submicrometer InGaAs depletion-mode MISFET with a self-aligned recessed gate structure is presented. The techniques used to implement this FET structure…”
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A new self-aligned recessed-gate InP MESFET by Cheng, C.L., Coldren, L.A., Miller, B.I., Liao, A.S.H., Leheny, R.F., Lalevic, B.

“…We describe a new self-aligned recessed-gate InP MESFET. In this structure, material selective and anisotropic etching properties of InP/InGaAsP system are…”
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An In0.53Ga0.47As p-channel MOSFET with plasma-grown native oxide insulated gate by Liao, A.S.H., Tell, B., Leheny, R.F., Nahory, R.E., DeWinter, J.C., Martin, R.J.

“…We describe the operation of an In 0.53 Ga 0.47 As p-channel inversion mode MOSFET with plasma grown native oxide insulated gate. This device exhibits a…”
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In0.53Ga0.47As/Si3N4n-channel and p-channel inversion mode MISFET's by Liao, A.S.H., Leheny, R.F., Nahory, R.E., DeWinter, J.C., Martin, R.J.

“…We describe the operation of both n-channel and p-channel Si 3 N 4 insulated gate In 0.53 Ga 0.47 As inversion mode MISFET's. These devices exhibit a maximum…”
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A planar embedded InGaAs photodiode on semi-insulating InP substrate for monolithically integrated PIN-FET receivers, using selective vapor phase epitaxy and ion implantation technique by Liao, A.S.H., Bridges, T.J., Burkhardt, E.G., Tell, B., Leheny, R.F., Beebe, E.D.

“…We report a new embedded InGaAs PIN photodetector structure on semi-insulating InP substrate, using selective VPE growth process and Be implantation technique…”
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Submicron self-aligned recessed gate InGaAs MISFET exhibiting very high transconductance by Cheng, C.L., Liao, A.S.H., Chang, T.Y., Leheny, R.F., Coldren, L.A., Lalevic, B.

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High transconductance InAlAs/InGaAs double heterostructure MESFETs with in-situ aluminum oxide gate barrier by Chang, T.Y., Behringer, R.E., Howard, R.E., Liao, A.S.H., Jackel, L.D., Caridi, E.A., Skocpol, W.J., Epworth, R.W.

“…By incorporating an in-situ aluminum oxide gate barrier in InAlAs/InGaAs double heterostructure FETs we have reduced the gate leakage current by more than an…”
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