Search Results - "Lewis, Dean L."

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) by Dae Hyun Kim, Athikulwongse, Krit, Healy, Michael B., Hossain, Mohammad M., Moongon Jung, Khorosh, Ilya, Kumar, Gokul, Young-Joon Lee, Lewis, Dean L., Tzu-Wei Lin, Chang Liu, Panth, Shreepad, Pathak, Mohit, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Loh, Gabriel H., Lee, Hsien-Hsin S., Sung Kyu Lim

“…This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked…”
Get full text

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth by Dong Hyuk Woo, Nak Hee Seong, Lewis, Dean L, Lee, Hsien-Hsin S

“…Memory bandwidth has become a major performance bottleneck as more and more cores are integrated onto a single die, demanding more and more data from the…”
Get full text

Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs by Xin Zhao, Lewis, D L, Lee, Hsien-Hsin S, Sung Kyu Lim

“…Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with…”
Get full text

Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores by Lewis, D. L., Panth, S., Xin Zhao, Sung Kyu Lim, Lee, H-H S.

“…3D integration is a promising new technology for tightly integrating multiple active silicon layers into a single chip stack. Both the integration of…”
Get full text

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory by Healy, M B, Athikulwongse, K, Goel, R, Hossain, M M, Kim, D H, Young-Joon Lee, Lewis, D L, Tzu-Wei Lin, Chang Liu, Moongon Jung, Ouellette, B, Pathak, M, Sane, H, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Loh, G H, Lee, H S, Sung Kyu Lim

“…We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication…”
Get full text

Design for pre-bond testability in 3D integrated circuits by Lewis, Dean L

“…In this dissertation we describe several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate…”
Get full text

Architectural evaluation of 3D stacked RRAM caches by Lewis, D.L., Lee, H.-H.S.

“…The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique…”
Get full text

Design for pre-bond testability in 3D integrated circuits by Lewis, Dean L

“…In this dissertation we describe several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate…”
Get full text

Pre-bond testable low-power clock tree design for 3D stacked ICs by Xin Zhao, Lewis, D.L., Lee, H.-H.S., Sung Kyu Lim

“…Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The overall yield of 3D ICs improves with pre-bond testability because…”
Get full text

Testing Circuit-Partitioned 3D IC Designs by Lewis, D.L., Lee, H.-H.S.

“…3D integration is an emerging technology that allows for the vertical stacking of multiple silicon die. These stacked die are tightly integrated with…”
Get full text

High Performance Non-blocking Switch Design in 3D Die-Stacking Technology by Lewis, D.L., Yalamanchili, S., Lee, H.-H.S.

“…Die stacking is a promising new technology that enables integration of devices in the third dimension. It allows the stacking of multiple active layers…”
Get full text